Solid state memory system with power management mechanism and method of operation thereof

Patent metadata

Field	Value
Publication number	US-10241701-B2
Application number	US-201514976309-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Sep 16, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A solid state memory system includes: an interface circuit; a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled between the device processor and the non-volatile memory array, configured to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command.

First claim

What is claimed is:

1. A solid state memory system comprising:
an interface circuit;
a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command and wherein the device processor is further configured to suspend background tasks, utilize only low power pages, update the metadata log with adjusted threshold for reduced voltage writes, and provide continued operation based on the dynamic power limit command;
a non-volatile memory array coupled to the interface circuit; and
a power manager unit, coupled to the device processor, configured by the device processor, wherein the device processor loads registers in the power manager unit to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command received by the device processor, the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded.

2. The system as claimed in claim 1 wherein the power manager unit is further configured to generate a limited power write/erase voltage over a longer time in response to the dynamic power limit command.

3. The system as claimed in claim 1 further comprising a volatile memory, coupled to the interface circuit, that is configured to communicate with the device processor for updating the metadata log.

4. The system as claimed in claim 1 wherein the power manager unit is further configured to modify the addressing of memory segments in the non-volatile memory array.

5. The system as claimed in claim 1 wherein the device processor is further configured to execute a shallow erase on the non-volatile memory array by a limited power write/erase voltage for a fixed time and storing an adjustment to a threshold voltage for 0 bit (V TH0 ), a threshold voltage for 1 bit (V TH1 ), a read voltage (V READ ), or a combination thereof.

6. The system as claimed in claim 1 wherein the device processor is further configured to access the metadata log for threshold voltage adjusted value for a threshold voltage for 0 bit (V TH0 ), a threshold voltage for 1 bit (V TH1 ), or a read voltage (V READ ) to address the non-volatile memory array.

7. The system as claimed in claim 1 wherein the power manager unit is further configured to monitor a power feedback for adjusting a limited power write/erase voltage to remain less than a limited power level.

8. The system as claimed in claim 1 wherein the device processor is further configured to execute the dynamic power limit command including configuring the non-volatile memory array for only performing least significant bit (LBS) writes to reduce a total power consumed.

9. The system as claimed in claim 1 wherein the device processor is further configured to use the metadata log for restoring the non-volatile memory array when the device processor detects the dynamic power limit command that indicates a full power and performance command.

10. The system as claimed in claim 1 wherein the device processor is further configured to limit the execution of a garbage collection task if required by the dynamic power limit command.

11. A method of operation of a solid state memory system comprising:
receiving a dynamic power limit command through an interface circuit for configuring a device processor to suspend background tasks, utilize only low power pages, update a metadata log with adjusted threshold for reduced voltage writes, and provide continued operation based on the dynamic power limit command;
configuring a power manager unit, by the device processor, wherein the device processor loads registers in the power manager unit, for altering a configuration of a non-volatile memory array for meeting a requirement of the dynamic power limit command received by the device processor, includes the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded; and
updating the metadata log with configuration data from the power manager unit.

12. The method as claimed in claim 11 further comprising generating a limited power write/erase voltage over a longer time in response to the dynamic power limit command.

13. The method as claimed in claim 11 wherein updating the metadata log includes the device processor communicating with the volatile memory.

14. The method as claimed in claim 11 further comprising modifying the addressing of memory segments in the non-volatile memory array.

15. The method as claimed in claim 11 further comprising executing a shallow erase on the non-volatile memory array by a limited power write/erase voltage for a fixed time and storing an adjustment to a threshold voltage for 0 bit (V TH0 ), a threshold voltage for 1 bit (V TH1 ), a read voltage (V READ ), or a combination thereof.

16. The method as claimed in claim 11 further comprising accessing the metadata log for threshold voltage adjusted value for a threshold voltage for 0 bit (V TH0 ), a threshold voltage for 1 bit (V TH1 ), or a read voltage (V READ ) for addressing the non-volatile memory array.

17. The method as claimed in claim 11 further comprising monitoring a power feedback for adjusting a limited power write/erase voltage less than a limited power level.

18. The method as claimed in claim 11 further comprising configuring the device processor for executing the dynamic power limit command including configuring the non-volatile memory array for only performing least significant bit (LBS) writes for reducing a total power consumed.

19. The method as claimed in claim 11 further comprising accessing the metadata log for restoring the non-volatile memory array based on the device processor receiving the dynamic power limit command indicating a full power and performance.

20. The method as claimed in claim 11 further comprising limiting executing a garbage collection task if required by the dynamic power limit command.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Inseok Stephen
• Ahn Byoung Young
• Ki Yang Seok

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F1/32

  Means for saving power · CPC title