Autonomously controlling a buffer of a processor

Patent metadata

Field	Value
Publication number	US-10241556-B2
Application number	US-201315025575-A
Country	US
Kind code	B2
Filing date	Nov 27, 2013
Priority date	Nov 27, 2013
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
an input/output (I/O) buffer coupled to a logic circuit of the apparatus;
a pad to couple an external device to the I/O buffer of the apparatus; and
a control logic circuit coupled to the I/O buffer to:
sample a state on the pad subsequent to a first entry into low power state of the apparatus;
determine a first control value for the I/O buffer based on the sampled state and the low power state of the apparatus;
store the first control value in a configuration storage associated with the I/O buffer;
in response to a second entry into the low power state of the apparatus, control the I/O buffer to maintain the sampled state at the pad using the stored first control value.

2. The apparatus of claim 1 , wherein the control logic circuit is to store the first control value and control the I/O buffer to maintain the sampled state in response to a determination that an override indicator is not active, and wherein the control logic circuit is to:
in response to a determination that the override indicator is active:
store a second control value in the configuration storage; and
control the I/O buffer to maintain an override value at the pad using the stored second control value, wherein the override value is a default value provided by a software driver.

3. The apparatus of claim 1 , wherein the configuration storage comprises a first field to store a first setting for a first switch coupled between a supply voltage node and an output node of the I/O buffer, wherein when closed the first switch is to enable a pullup impedance to couple to the output node.

4. The apparatus of claim 3 , wherein the configuration storage comprises a second field to store a second setting for a second switch coupled between a reference voltage node and the output node of the I/O buffer, wherein when closed the second switch is to enable a pulldown impedance to couple to the output node.

5. The apparatus of claim 4 , wherein the configuration storage comprises a third field to store a third setting to enable a transmitter of the I/O buffer.

6. The apparatus of claim 1 , the control logic circuit to place the pad into a tri-state before sampling the state of the pad.

7. The apparatus of claim 1 , wherein the I/O buffer comprises:
a transmitter to receive a signal and to output the signal to the pad;
a pullup resistance configured to be controllably coupled between a supply voltage node and an output node of the transmitter; and
a pulldown resistance configured to be controllably coupled between a reference voltage node and the output node of the transmitter.

8. The apparatus of claim 7 , wherein the I/O buffer further comprises a receiver to receive a second signal from the pad and to output the signal to the logic unit.

9. A system comprising:
a processor formed in an integrated circuit (IC), the processor including:
at least one core;
an input/output (I/O) controller having a power management logic circuit; and
at least one input/output (I/O) buffer coupled to the I/O controller to communicate signal information with one or more devices coupled to the processor,
wherein the power management logic circuit is to:
receive an indication of a first entry into a low power state of at least a portion of the processor,
responsive the first entry, sample a state on a pad of the IC, the pad coupled between the at least one I/O buffer and an interconnect,
determine a first control value for the at least one I/O buffer based on the sampled state and the low power state,
store the first control value in a configuration storage associated with the I/O buffer,
in response to a second entry into the low power state, control the I/O buffer to maintain the sampled state at the pad using the stored first control value; and

a dynamic random access memory (DRAM) coupled to the processor.

10. The system of claim 9 , wherein the power management logic circuit is to set a field of the configuration storage responsive to the sampled value, to cause coupling of at least one of a first impedance and a second impedance to an output node of the at least one I/O buffer.

11. The system of claim 10 , wherein the power management logic circuit is to:
sample the value, determine the first control value, and cause the coupling in response to a determination that an override indicator is not active; and
in response to a determination that the override indicator is active, cause the coupling based on an override value, wherein the override value is provided by a firmware or a software driver.

12. The system of claim 11 , wherein the power management logic circuit is to cause coupling of the first impedance or the second impedance to enable the I/O buffer to output a signal corresponding to the sampled value.

13. A method comprising:
responsive to a first entry into a low power state, sampling a state on a pad of an integrated circuit (IC) coupled to an interconnect, the pad coupled to a buffer of the IC, the buffer including a transmitter and a receiver;
selecting a first control value for at least one controllable element of the buffer based on the sampled state and the low power state;
storing the selected first control value in a storage associated with the buffer; and
in response to a second entry into the low power state, controlling the buffer to maintain the sampled state at the pad using the stored first control value.

14. The method of claim 13 , further comprising:
determining whether an override indicator is active;
in response to a determination that the override indicator is active:
store a second control value in the configuration storage; and
control the I/O buffer to maintain an override value at the pad using the second control value,

wherein storing the first control value and controlling the buffer to maintain the sampled state are performed in response to a determination that an override indicator is not active.

15. The method of claim 14 , further comprising receiving the override indicator from a firmware of the system.

16. The method of claim 13 , further comprising controlling the buffer to place the pad into a tri-state before sampling the state.

17. The method of claim 13 , wherein the storage comprises a plurality of fields including:
a first field to store a first setting for a first switch coupled between a supply voltage node and an output node of the buffer;
a second field to store a second setting for a second switch coupled between a reference voltage node and the output node of the buffer;
a third field to store a third setting for a transmitter of the buffer; and
a fourth field to store a fourth setting for a receiver of the buffer.

18. The method of claim 13 , further comprising storing the sampled state in a second storage, and thereafter referencing the sampled state.

19. The method of claim 13 , further comprising controlling the buffer to couple a pulldown impedance to the pad when the pad is unused in a platform including the IC.

Assignees

• Intel Corp

Inventors

• Elias Vinu K
• Ramani Sundar
• Tomar Arvind S
• Liu Jianjun

Classifications

• H03K19/018592

  with a bidirectional operation · CPC title

• H03K19/018585 Primary

  programmable · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title