Semiconductor optical integrated device including a reduced thickness upper cladding layer in a ridge waveguide portion, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10241267-B2
Application number	US-201715423082-A
Country	US
Kind code	B2
Filing date	Feb 2, 2017
Priority date	Oct 6, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A semiconductor optical integrated device includes: a substrate; at least a lower cladding layer, a waveguide core layer, and an upper cladding layer sequentially layered on the substrate, a buried hetero structure waveguide portions each having a waveguide structure in which a semiconductor cladding material is embedded near each of both sides of the waveguide core layer; and a ridge waveguide portion having a waveguide structure in which a semiconductor layer including at least the upper cladding layer protrudes in a mesa shape. Further, a thickness of the upper cladding layer in each of the buried hetero structure waveguide portions is greater than a thickness of the upper cladding layer in the ridge waveguide portion.

First claim

What is claimed is:

1. A semiconductor optical integrated device comprising:
a substrate;
at least a lower cladding layer, a waveguide core layer, and an upper cladding layer sequentially layered on the substrate;
a buried hetero structure waveguide portion having a waveguide structure in which a semiconductor cladding material is embedded near each of both sides of the waveguide core layer; and
a ridge waveguide portion having a waveguide structure in which a semiconductor layer including at least the upper cladding layer protrudes in a mesa shape,
wherein a thickness of the upper cladding layer in the buried hetero structure waveguide portion is greater than a thickness of the upper cladding layer in the ridge waveguide portion, and
wherein an intermediate layer, which has different etching resistance from that of the upper cladding layer and has slower etching speed than that of the upper cladding layer, is inserted in the upper cladding layer in the buried hetero structure waveguide portion.

2. The semiconductor optical integrated device according to claim 1 , wherein
the ridge waveguide portion has a deep ridge waveguide structure in which a semiconductor layer including the waveguide core layer protrudes in the mesa shape.

3. The semiconductor optical integrated device according to claim 1 , further comprising
an end-face window structure portion having a window structure in which a region adjacent to the buried hetero structure waveguide portion is filled with a semiconductor cladding material instead of the waveguide core layer.

4. The semiconductor optical integrated device according to claim 1 , wherein
the buried hetero structure waveguide portion is a spot size converter which gradually converts a spot size of light propagated in a waveguide.

5. The semiconductor optical integrated device according to claim 1 , wherein
the waveguide core layer of the buried hetero structure waveguide portion is thinner than the waveguide core layer of the ridge waveguide portion.

6. The semiconductor optical integrated device according to claim 1 , wherein
the intermediate layer is an etching stop layer.

7. The semiconductor optical integrated device according to claim 1 , wherein
the buried hetero structure waveguide portion includes at least an optical amplifier, and
the ridge waveguide portion includes at least a modulator.

8. The semiconductor optical integrated device according to claim 1 , wherein
the buried hetero structure waveguide portion includes at least a plurality of laser oscillators, and
the ridge waveguide portion includes at least an arrayed waveguide grating.

9. A method of manufacturing a semiconductor optical integrated device which includes a buried hetero structure waveguide portion and a ridge waveguide portion, the method comprising:
a first step of layering at least a lower cladding layer and a waveguide core layer on a substrate in a region where the buried hetero structure waveguide portion is to be formed and a region where the ridge waveguide portion is to be formed;
a second step of etching a semiconductor layer which includes the waveguide core layer in a mesa shape in the region where the buried hetero structure waveguide portion is to be formed;
a third step of embedding a semiconductor cladding material near both sides of the waveguide core layer in the region where the buried hetero structure waveguide portion is to be formed;
a fourth step of layering a semiconductor layer, which includes at least an upper cladding layer, in the region where the buried hetero structure waveguide portion is to be formed and the region where the ridge waveguide portion is to be formed;
a fifth step of performing etching to remove a part of the upper cladding layer in the region where the ridge waveguide portion is to be formed; and
a sixth step of removing both sides of the waveguide core layer in the regions where the ridge waveguide portion is to be formed and etching the semiconductor layer which includes at least the upper cladding layer in a mesa shape, in this order.

10. The method of manufacturing the semiconductor optical integrated device according to claim 9 , wherein
the fourth step includes a step of inserting an etching stop layer which has different etching resistance from that of the upper cladding layer to stop the etching in the fifth step.

11. The method of manufacturing the semiconductor optical integrated device according to claim 9 , further comprising
a step of layering a contact layer on the upper cladding layer between the fifth step and the sixth step.

12. The method of manufacturing the semiconductor optical integrated device according to claim 9 , wherein the fifth step includes performing etching to remove the part of the upper cladding layer in the region where the ridge waveguide portion is to be formed so that a thickness of the upper cladding layer in the buried hetero structure waveguide portion is greater than a thickness of the upper cladding layer in the ridge waveguide portion.

Assignees

• Furukawa Electric Co Ltd

Inventors

• Kiyota Kazuaki
• Kimoto Tatsuya
• Saito Yusuke

Classifications

• H01S5/50

  Amplifier structures not provided for in groups H01S5/02 - H01S5/30 · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• G02B6/122 Primary

  Basic optical elements, e.g. light-guiding paths · CPC title

• H01S5/2232

  with inner confining structure between the active layer and the lower electrode · CPC title

• G02B6/12011

  characterised by the arrayed waveguides, e.g. comprising a filled groove in the array section · CPC title