Semiconductor device manufacturing method and semiconductor device

Patent metadata

Field	Value
Publication number	US-10236374-B2
Application number	US-201815919665-A
Country	US
Kind code	B2
Filing date	Mar 13, 2018
Priority date	Feb 16, 2015
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p− type drift layer comprised of the area in which the p type impurity is introduced, as well as an n− type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

First claim

What is claimed is:

1. A semiconductor device manufacturing method comprising the steps of:
(a) preparing a p type semiconductor substrate;
(b) epitaxially growing an n type semiconductor film over the semiconductor substrate;
(c) implanting ions of a p type first impurity into a first area of the semiconductor film and not implanting ions of the first impurity into a second area of the semiconductor film, the second area being adjacent to the first area, to form a p type first semiconductor region comprised of the first area in which the first impurity is introduced, as well as a n type second semiconductor region comprised of the second area in which the first impurity is not introduced;
(d) forming a first groove that reaches the middle of the first semiconductor region from the upper surface of the semiconductor film;
(e) forming a gate insulating film in an inner wall of the first groove;
(f) forming a gate electrode over the gate insulating film so as to fill the first groove;
(g) forming an n type third semiconductor region in the upper part of the first semiconductor region as well as the upper part of the second semiconductor region;
(h) forming a p type fourth semiconductor region in the upper part of the third semiconductor region;
(i) forming a source electrode contacting the third and fourth semiconductor regions; and
(j) forming a drain electrode electrically coupled to the semiconductor substrate,
wherein a transistor is formed by the first semiconductor region, the third semiconductor region, the fourth semiconductor region, the gate insulating film, and the gate electrode.

2. The semiconductor device manufacturing method according to claim 1 ,
wherein the first semiconductor region formed in the (c) step is brought into contact with the semiconductor substrate.

3. The semiconductor device manufacturing method according to claim 1 ,
wherein the semiconductor film in which the n type second impurity is introduced is epitaxially grown in the (b) step,
wherein the n type second semiconductor region comprised of the second area in which the second impurity is introduced and the first impurity is not introduced is formed in the (c) step,
wherein the third semiconductor region is formed by implanting ions of an n type third impurity into the upper part of the first semiconductor region and into the upper part of the second semiconductor region in the (g) step, and
wherein the concentration of the third impurity in the third semiconductor region that is formed in the (g) step is higher than the concentration of the second impurity in the second semiconductor region that is formed in the (c) step.

4. The semiconductor device manufacturing method according to claim 1 ,
wherein the (c) step comprises the steps of:
(c1) covering the second area by a mask film and exposing the first area from the mask film;
(c2) forming the first semiconductor region and the second semiconductor region by implanting ions of the first impurity into the first area exposed from the mask film, and by not implanting ions of the first impurity into the second area covered by the mask film; and
(c3) removing the mask film covering the second area after the (c2) step.

5. The semiconductor device manufacturing method according to claim 1 ,
wherein the (i) step comprises the steps of:
(i1) forming a second groove passing through the fourth semiconductor region and reaching the third semiconductor region; and
(i2) forming the source electrode so as to fill the second groove.

6. The semiconductor device manufacturing method according to claim 1 ,
wherein the semiconductor film is epitaxially grown over a first main surface of the semiconductor substrate in the (b) step,
wherein the drain electrode is formed over a second main surface opposite the first surface of the semiconductor substrate in the (j) step.

7. The semiconductor device manufacturing method according to claim 5 ,
wherein the second groove is formed passing through the fourth semiconductor region and reaching the part of the third semiconductor region that is located above the second semiconductor region in the (i1) step.

8. The semiconductor device manufacturing method according to claim 1 ,
wherein an inverter is formed by the transistor.

9. The semiconductor device manufacturing method according to claim 1 ,
wherein the lower surface of the third semiconductor region is higher than the bottom of the first groove.

10. The semiconductor device manufacturing method according to claim 1 ,
wherein the third semiconductor region and the fourth semiconductor region are brought into contact with the gate insulating film.

Assignees

• Renesas Electronics Corp

Inventors

• Ohtani Kinya
• Nishimura Yasuhiro

Classifications

• H10P30/22

  using masks · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title