Tunnel transistors with abrupt junctions

Patent metadata

Field	Value
Publication number	US-10236344-B2
Application number	US-201514887413-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Apr 30, 2012
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.

First claim

What is claimed is:

1. A tunnel field effect transistor (TFET) device, comprising:
a substrate layer comprising a substrate material;
a source layer comprising a source material disposed upon the substrate layer, wherein the source material comprises a first conductivity;
a drain layer comprising a drain material disposed upon the substrate layer, wherein the drain material comprises a second conductivity;
a first and a second sidewall spacer, wherein the first sidewall spacer comprises a first layer of a spacer material disposed upon the source layer, and wherein the second sidewall spacer comprises a second layer of the spacer material disposed upon the drain layer; and
a gate stack interposed between the first and the second sidewall spacers and further interposed between the source layer and the drain layer, wherein the gate stack extends from between the first and the second sidewall spacers, and from between the source layer and the drain layer, into a recess cavity of the substrate layer;
wherein the gate stack comprises a gate layer of a gate material, a channel layer of a channel material, and a gate dielectric layer of a first dielectric material;
wherein the gate layer and the gate dielectric layer are interposed between the first and second sidewall spacers;
wherein the gate layer, the gate dielectric layer, and the channel layer are interposed between the source layer and the drain layer and extend into the recess cavity of the substrate layer;
wherein the gate dielectric layer is interposed between the gate layer and the first sidewall spacer, between the gate layer and the second sidewall spacer, and between the gate layer and the channel layer;
wherein the channel layer is interposed between the gate dielectric layer and the source layer, between the gate dielectric layer and the drain layer, and inside the recess cavity of the substrate layer;
wherein the gate dielectric layer extends, within the gate stack, above a first top portion of the channel layer between, and in contact with each of, the gate layer and the first sidewall spacer, and above a second top portion of the channel layer between, and in contact with each of, the gate layer and second sidewall spacer; and
wherein outer boundaries of the gate dielectric layer and outer boundaries of the channel layer are planarized.

2. The TFET device of claim 1 , further comprising a first and a second interlayer dielectric, wherein the first interlayer dielectric comprises a first planarized layer of a second dielectric material disposed upon the source layer, wherein the second interlayer dielectric comprises a second planarized layer of the second dielectric material disposed upon the drain layer, wherein the first interlayer dielectric is disposed upon the source layer adjacent to and in contact with the first sidewall spacer opposite the gate stack, and wherein the second interlayer dielectric is disposed upon the drain layer adjacent to and in contact with the second sidewall spacer opposite the gate stack.

3. The TFET device of claim 2 , wherein the second dielectric material is selected from the group consisting of silicon dioxide and silicon nitride.

4. The TFET device of claim 1 , wherein the source material comprises an n+ doped material, and wherein the drain material comprises a p+ doped material.

5. The TFET device of claim 1 , wherein the source material comprises a p+ doped material, and wherein the drain material comprises an n+ doped material.

6. The TFET device of claim 5 , wherein the p+ doped material comprises a germanium material selected from the group consisting of SiGe and germanium.

7. The TFET device of claim 5 , wherein the n+ doped material comprises a material selected from the group consisting of n+ doped SiP and n+ doped SiCP.

8. The TFET device of claim 1 , wherein the spacer material comprises silicon nitride.

9. The device of claim 1 , wherein the gate stack comprises an anisotropic geometry between the source layer and the drain layer and extending into the substrate layer.

10. The device of claim 1 , wherein the gate stack comprises an isotropic geometry between the source layer and the drain layer and extending into the substrate layer.

11. The device of claim 1 , wherein the gate stack comprises a sigma geometry between the source layer and the drain layer and extending into the substrate layer.

12. The TFET device of claim 1 , wherein the gate dielectric layer has a thickness of between 1 and 2 nanometers, and wherein the first dielectric material comprises a high-k dielectric material.

13. The TFET device of claim 1 , wherein the gate material comprises a metal material that includes at least one of TiN, TaN, TiAl, Ti, Ta, W, Al, Dy, and Er.

Assignees

• IBM

Inventors

• Alptekin Emre
• Tran Hung H
• Vega Reinaldo A
• Yuan Xiaobin

Classifications

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316 Primary

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/01324 Primary

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H01L29/66356

  Electricity · mapped topic