Solid-state imaging element and electronic device to improve quality of an image

US10236311B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10236311-B2
Application numberUS-201515518483-A
CountryUS
Kind codeB2
Filing dateOct 7, 2015
Priority dateOct 20, 2014
Publication dateMar 19, 2019
Grant dateMar 19, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.

First claim

Opening claim text (preview).

The invention claimed is: 1. A solid-state imaging element, comprising: a wiring layer, and a photoelectric conversion unit configured to photoelectrically convert incident light incident from incident surface of the photoelectric conversion unit, wherein the photoelectric conversion unit includes a plurality of patterns, wherein positions of the plurality of patterns with respect to the wiring layer are misaligned from each other along a straight line in an extending direction of the wiring layer, wherein the wiring layer is on a bottom surface side of the photoelectric conversion unit, wherein the bottom surface side is opposite to the incident surface, and wherein the wiring layer includes a protruding pattern on a surface that faces the photoelectric conversion unit. 2. The solid-state imaging element according to claim 1 , wherein the plurality of patterns are at different intervals in the extending direction of the wiring layer. 3. The solid-state imaging element according to claim 1 , wherein a pixel in a proximity to an outer periphery of the solid-state imaging element has a lower density of patterns in a direction vertical to a side of the outer periphery. 4. The solid-state imaging element according to claim 1 , wherein each of the positions of the plurality of patterns is different than a position of a first wire of the wiring layer, wherein the position of the first wire is closer to the photoelectric conversion unit than a position of a second wire, and wherein the second wire includes a set of patterns of the plurality of patterns. 5. The solid-state imaging element according to claim 1 , wherein a width of each of the plurality of patterns is based on a width of the wiring layer. 6. The solid-state imaging element according to claim 1 , wherein a pixel in proximity to a side of an outer periphery of the solid-state imaging element includes a set of patterns of the plurality of patterns, and wherein a length corresponding to the set of patterns in the extending direction of the wiring layer is greater than a threshold length. 7. The solid-state imaging element according to claim 1 , wherein the wiring layer comprises a plurality of wires, wherein the plurality of patterns are not formed in a specific wire of the plurality of wires of the wiring layer, and wherein the specific wire is closest to a bottom surface of the photoelectric conversion unit among the plurality of wires. 8. The solid-state imaging element according to claim 1 , wherein the plurality of patterns are in the photoelectric conversion unit of a pixel that receives light of a specific wavelength or more. 9. The solid-state imaging element according to claim 1 , wherein an arrangement of the plurality of patterns is based on at least one of a connection of wires of adjacent wiring layers or a connection of a wire of the wiring layer to a semiconductor substrate of the photoelectric conversion unit. 10. An electronic device, comprising: a solid-state imaging element that comprises: a wiring layer; and a photoelectric conversion unit configured to photoelectrically convert incident light incident from incident surface of the photoelectric conversion unit, wherein the photoelectric conversion unit includes a plurality of patterns, and wherein positions of the plurality of patterns with respect to the wiring layer are misaligned from each other along a straight line in an extending direction of the wiring layer, wherein the wiring layer is on a bottom surface side of the photoelectric conversion unit, wherein the bottom surface side is opposite to the incident surface, and wherein the wiring layer includes a protruding pattern on a surface that faces the photoelectric conversion unit.

Assignees

Inventors

Classifications

  • based on the phase difference signals · CPC title

  • Pixels specially adapted for focusing, e.g. phase difference pixel sets · CPC title

  • Addressed sensors, e.g. MOS or CMOS sensors · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10236311B2 cover?
The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged o…
Who is the assignee on this patent?
Sony Semiconductor Solutions Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/14609. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 19 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).