Display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10236309-B2
Application number	US-201715783820-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Oct 14, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A display device according to an exemplary embodiment includes: a substrate including a pixel area and a transmission area adjacent to the pixel area; a transistor positioned on the substrate in the pixel area; a planarization layer positioned on the transistor in the pixel area; a wall positioned on the substrate between the pixel area and the transmission area; and a pixel electrode positioned on the planarization layer and extending in a trench between the planarization layer and the wall.

First claim

What is claimed is:

1. A display device comprising:
a substrate including a pixel area and a transmission area adjacent to the pixel area, the transmission area comprising a transmission window;
a transistor positioned on the substrate in the pixel area;
a planarization layer positioned on the transistor in the pixel area;
a wall positioned on the substrate between the pixel area and the transmission area; and
a pixel electrode positioned on the planarization layer and extending in a trench between the planarization layer and the wall, the pixel electrode positioned to not overlap with the transmission area.

2. The display device of claim 1 , wherein
the wall and the planarization layer are formed of a same material.

3. The display device of claim 1 , wherein
an edge of the pixel electrode is positioned in the trench.

4. The display device of claim 3 , further comprising
a pixel definition layer positioned on the pixel electrode,
wherein the pixel definition layer covers the edge of the pixel electrode in the trench.

5. The display device of claim 1 , wherein
the wall is separated from the planarization layer.

6. The display device of claim 1 , further comprising
a gate insulating layer positioned between a semiconductor of the transistor and a gate electrode of the transistor, and
wherein the wall is positioned directly on the gate insulating layer.

7. The display device of claim 6 , wherein
the pixel electrode is in contact with the gate insulating layer in the trench.

8. The display device of claim 7 , further comprising
a light emission member positioned on the pixel electrode and a common electrode positioned on the light emission member,
wherein the common electrode is in contact with one side of the wall.

9. The display device of claim 8 , wherein
the light emission member is positioned between the gate insulating layer and the common electrode in the transmission area.

10. The display device of claim 7 , further comprising
a light emission member positioned on the pixel electrode and a common electrode positioned on the light emission member,
wherein the common electrode is in contact with the gate insulating layer in the transmission area.

11. The display device of claim 1 , wherein
the wall is connected to the planarization layer.

12. The display device of claim 1 , further comprising
an interlayer insulating layer positioned between a gate electrode of the transistor and source and drain electrodes, and
the wall is positioned directly on the interlayer insulating layer.

13. The display device of claim 1 , wherein
the display device is a transparent display.

14. A method for manufacturing a display device, comprising:
forming a transistor in a pixel area on a substrate including the pixel area and a transmission area adjacent to the pixel area, the transmission area comprising a transmission window;
depositing and etching an insulating material in the pixel area and the transmission area to form a planarization layer in the pixel area and to form a wall between the pixel area and the transmission area; and
depositing and etching a conductive material to form a pixel electrode positioned on the planarization layer and extending in a trench between the wall and the planarization layer,
wherein the pixel electrode is positioned to not overlap the transmission area.

15. The method of claim 14 , wherein
the pixel electrode is formed for an edge to be positioned in the trench.

16. The method of claim 14 , further comprising
depositing and etching an insulating material on the pixel electrode to form a pixel definition layer covering the pixel electrode in the trench.

17. The method of claim 14 , further comprising
forming a gate insulating layer on the substrate,
wherein the step of forming the transistor includes depositing and etching a conductive material on the gate insulating layer to form a gate electrode, and
the pixel electrode is formed to be in contact with the gate insulating layer in the trench.

18. The method of claim 14 , wherein
an etching preventing layer is formed in the transmission area when forming the gate electrode.

19. The method of claim 14 , further comprising
forming a light emission member on the pixel electrode and forming a common electrode on the light emission member,
wherein the common electrode is formed to be in contact with one side of the wall.

20. The method of claim 14 , further comprising
forming a gate insulating layer on the substrate; and
forming a light emission member on the pixel electrode and forming a common electrode on the light emission member,
wherein the common electrode is formed to be in contact with the gate insulating layer in the transmission area.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Jong Yun

Classifications

• H01L27/1262

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic

• H01L27/1248 Primary

  Electricity · mapped topic

• H01L27/3262

  Electricity · mapped topic

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title