Method of forming patterns for semiconductor device

Patent metadata

Field	Value
Publication number	US-10236185-B2
Application number	US-201715686578-A
Country	US
Kind code	B2
Filing date	Aug 25, 2017
Priority date	Nov 25, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.

First claim

What is claimed is:

1. A method of forming patterns for a semiconductor device, the method comprising:
preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, and a solvent;
applying the hardmask composition to an etching target layer, the etching target layer including a plurality of openings exposing an underlying substrate;
forming a hardmask by heat-treating the applied hardmask composition;
forming a photoresist pattern on the hardmask;
forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask; and
forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask;
wherein an average size of the plurality of openings is less than an average length of the carbon allotrope.

2. The method of claim 1 , wherein, in the preparing the hardmask composition, the carbon allotrope is dispersed by the solvent, and the SOH material is dissolved by the solvent.

3. The method of claim 2 , wherein, in the preparing the hardmask composition, the hardmask composition further comprises an additive including a cross-linker, a radical stabilizer, a surfactant, a pH regulator, or a combination thereof.

4. The method of claim 1 , wherein, in the preparing the hardmask composition, the carbon allotrope includes a fullerene, a carbon nanotube, graphene, carbon black, or a combination thereof.

5. The method of claim 1 , wherein, in the preparing the hardmask composition, the carbon allotrope has an average diameter of 1 nm to 50 nm, an average length of 100 nm to 300 nm, and a metal impurity content of 100 ppm or less.

6. The method of claim 1 , wherein, in the preparing the hardmask composition, the carbon allotrope includes a single wall structure, a double wall structure, a multiple wall structure, or a combination thereof.

7. The method of claim 1 , wherein, in the preparing the hardmask composition, the solvent includes at least one of propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), cyclohexanone, and ethyl lactate.

8. The method of claim 1 , wherein, the applying the hardmask composition applies the hardmask composition by a spin-on coating method.

9. The method of claim 1 , wherein, in the preparing the hardmask composition, a weight ratio of the carbon allotrope to the SOH material is 1:9 to 2:8.

10. The method of claim 1 , wherein, in the forming the etched pattern, the etched pattern includes a hole pattern.

11. A method of forming patterns for a semiconductor device, the method comprising:
forming an etching target layer including an uneven pattern on a substrate, the uneven pattern including a plurality of openings;
applying a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, and a solvent on the etching target layer;
forming a hardmask by heat-treating the applied hardmask composition;
sequentially forming an anti-reflection coating layer and a photoresist pattern on the hardmask; and
forming a hardmask pattern by etching the anti-reflection coating layer and the hardmask using the photoresist pattern as an etching mask;
wherein an average diameter of the plurality of opening is less than an average length of the carbon allotrope.

12. The method of claim 11 , wherein, in the applying the hardmask composition, the carbon allotrope is dispersed by the solvent, and the SOH material is dissolved by the solvent.

13. The method of claim 11 , wherein, in the forming the hardmask, the hardmask covers the uneven pattern, and an upper surface of the hardmask is substantially flat.

14. The method of claim 11 , wherein, in the forming the etching target layer, the plurality of openings are exposed at an upper surface of the etching target layer.

15. The method of claim 11 , further comprising:
forming an etched pattern having a shape different from that of the uneven pattern by etching the etching target layer using the hardmask pattern as an etching mask after the forming the hardmask pattern.

16. A method of manufacturing an integrated circuit device comprising:
forming a device isolation layer in a substrate to define a plurality of active regions;
forming an etching target layer on the substrate, the etching target layer including a plurality of openings;
preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, and a solvent;
applying the hardmask composition to the etching target layer;
forming a hardmask by heat-treating the applied hardmask composition;
forming a photoresist pattern on the hardmask;
forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask; and
forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask;
wherein an average size of the plurality of openings is less than an average length of the carbon allotrope.

17. The method of claim 16 , wherein, in the preparing the hardmask composition, the carbon allotrope is dispersed by the solvent, and the SOH material is dissolved by the solvent.

18. The method of claim 17 , wherein, in the preparing the hardmask composition, the hardmask composition further comprises an additive including a cross-linker, a radical stabilizer, a surfactant, a pH regulator, or a combination thereof.

19. The method of claim 16 , wherein, in the preparing the hardmask composition, the carbon allotrope includes a fullerene, a carbon nanotube, graphene, carbon black, or a combination thereof.

20. The method of claim 16 , wherein, in the preparing the hardmask composition, the carbon allotrope has an average diameter of 1 nm to 50 nm, an average length of 100 nm to 300 nm, and a metal impurity content of 100 ppm or less.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Yool
• Park Kyoung-Sil
• Choi Yun-Seok
• Kim Boo-Deuk
• Kim Ye-Hwan

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title