Dual-bit ROM cell with virtual ground line and programmable metal track

Patent metadata

Field	Value
Publication number	US-10236071-B1
Application number	US-201715700152-A
Country	US
Kind code	B1
Filing date	Sep 10, 2017
Priority date	Sep 10, 2017
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

First claim

The invention claimed is:

1. A read-only memory (ROM) device, comprising:
a plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, wherein each memory cell stores two bits of data, and wherein first and second memory cells of the plurality of memory cells are adjacent to each other, have a common drain terminal, and are arranged in a first column of the plurality of columns;
a plurality of bit-line pairs disposed vertically and associated with the plurality of columns, wherein a first bit-line pair of the plurality of bit-line pairs is associated with the first column;
a virtual ground line disposed vertically and shared by the first column and a second column of the plurality of columns, wherein the second column is adjacent to the first column;
a first programmable metal track disposed horizontally, that connects the first memory cell to the virtual ground line, wherein the first programmable metal track is defined based on a value of the two data bits stored in the first memory cell; and
a plurality of non-programmable metal tracks corresponding to the plurality of memory cells and disposed horizontally, wherein a first non-programmable metal track is connected to one of a source terminal and a drain terminal of the first memory cell by way of a metal contact, wherein the first non-programmable metal track connects the first memory cell to the first bit-line pair, and wherein the first programmable metal track connects the first memory cell to the virtual ground line by way of the first non-programmable metal track.

2. The ROM device of claim 1 , wherein the first memory cell includes a transistor for storing the two bits of data.

3. The ROM device of claim 2 , wherein the transistor is an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor.

4. The ROM device of claim 1 , wherein the virtual ground line is disposed between the first bit-line pair and a second bit-line pair of the plurality of bit-line pairs, and wherein the second bit-line pair is associated with the second column.

5. The ROM device of claim 1 , further comprising a virtual ground generation circuit that controls voltage levels of the first bit-line pair to read the two bits of data stored in the first memory cell.

6. The ROM device of claim 5 , wherein the two bits of data stored in the first memory cell is read by way of the virtual ground line and the first bit-line pair.

7. The ROM device of claim 6 , wherein the virtual ground generation circuit grounds a first bit-line of the first bit-line pair to read a first bit of the two bits of data stored in the first memory cell, and wherein the first bit is read on a second bit-line of the first bit-line pair.

8. The ROM device of claim 7 , wherein the virtual ground generation circuit grounds the second bit-line to read a second bit of the two bits of data stored in the first memory cell, and wherein the second bit is read on the first bit-line.

9. A read-only memory (ROM) device, comprising:
a plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, wherein each memory cell stores dual-bit data, and wherein first and second memory cells of the plurality of memory cells are adjacent to each other, have a common drain terminal, and are arranged in a first column of the plurality of columns;
a plurality of bit-line pairs that are disposed vertically and associated with the plurality of columns, wherein a first bit-line pair of the plurality of bit-line pairs is associated with the first column;
a virtual ground line disposed vertically, and shared between the first column and a second column of the plurality of columns, wherein the second column is adjacent to the first column;
a first programmable metal track disposed horizontally, that connects the first memory cell to the virtual ground line, wherein the first programmable metal track is defined based on a value of the two data bits stored in the first memory cell;
a second programmable metal track disposed horizontally, that connects the first memory cell to a first bit-line of the first bit-line pair, wherein the second programmable metal track is defined based on the value of the two data bits stored in the first memory cell; and
a plurality of non-programmable metal tracks corresponding to the plurality of memory cells and disposed horizontally,
wherein a first non-programmable metal track is connected to one of a source terminal and a drain terminal of the first memory cell by way of a metal contact, and the first non-programmable metal track connects the first memory cell to a second bit-line of the first bit-line pair, and
wherein the first programmable metal track connects the first memory cell to the virtual ground line by way of the first non-programmable metal track, and the second programmable metal track connects the first memory cell to the first bit-line by way of the first non-programmable metal track.

10. The ROM device of claim 9 , wherein the first memory cell includes a transistor for storing the two bits of data.

11. The ROM device of claim 10 , wherein the transistor is at least one of an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor.

12. The ROM device of claim 9 , wherein the virtual ground line is disposed between the first bit-line pair and a second bit-line pair of the plurality of bit-line pairs, and wherein the second bit-line pair is associated with the second column.

13. The ROM device of claim 9 , further comprising a virtual ground generation circuit that controls voltage levels of the first bit-line pair to read the two bits of data stored in the first memory cell.

14. The ROM device of claim 13 , wherein the two bits of data stored in the first memory cell is read by way of the virtual ground line and the first bit-line pair.

15. The ROM device of claim 14 , wherein the virtual ground generation circuit grounds the first bit-line to read a first bit of the two bits of data stored in the first memory cell, and wherein the first bit is read on a second bit-line of the first bit-line pair.

16. The ROM device of claim 15 , wherein the virtual ground generation circuit grounds the second bit-line to read a second bit of the two bits of data stored in the first memory cell, and wherein the second bit is read on the first bit-line.

Assignees

• Nxp Bv

Inventors

• Kohli Rajat
• Van De Steeg Patrick
• Mishra Jwalant Kumar
• Agarwal Pankaj

Classifications

• G11C11/40

  using transistors · CPC title

• G11C17/126 Primary

  Virtual ground arrays · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/5692

  read-only digital stores using storage elements with more than two stable states · CPC title