Write enable circuit, access switching circuit and analog-to-digital converter unit

Patent metadata

Field	Value
Publication number	US-10235308-B2
Application number	US-201415532575-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 5, 2014
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.

First claim

The invention claimed is:

1. A write enable circuit that outputs a write enable signal for digital data obtained by analog-to-digital conversion, in an analog-to-digital converter unit comprising a bus control unit connected to an external unit, an arithmetic processing unit to perform data processing, and an arithmetic unit to hold the digital data, and having a normal access mode in which the digital data are temporarily written into the arithmetic processing unit and then written into the bus control unit and a high-speed access mode in which the digital data are written directly into the bus control unit, the write enable circuit comprising:
an address coincidence determining circuit provided in the arithmetic unit to output a write enable signal from the arithmetic unit when a predetermined address for a memory of the bus control unit coincides with an address designated by the arithmetic processing unit; and
a logic circuit to input the write enable signal to the bus control unit only when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.

2. An access switching circuit that switches an access mode, in an analog-to-digital converter unit comprising a bus control unit connected to an external unit, an arithmetic processing unit to perform data processing, and an arithmetic unit to hold digital data obtained by analog-to-digital conversion, and having a normal access mode in which the digital data are temporarily written into the arithmetic processing unit and then written into the bus control unit and a high-speed access mode in which the digital data are written directly into the bus control unit, the access switching circuit comprising:
a logical OR circuit to perform an OR operation of a normal access signal indicating that now is in the normal access mode and a high-speed access signal indicating that now is in the high-speed access mode, which are outputted by the arithmetic processing unit, and output a result of the OR operation to the bus control unit;
a first logic circuit to input a read signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal; and
a second logic circuit to input a write signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal.

3. An analog-to-digital converter unit comprising a bus control unit connected to an external unit, an arithmetic processing unit to perform data processing, and an arithmetic unit to hold digital data obtained by analog-to-digital conversion, and having a normal access mode in which the digital data are temporarily written into the arithmetic processing unit and then written into the bus control unit and a high-speed access mode in which the digital data are written directly into the bus control unit, the analog-to-digital converter unit comprising:
a logical OR circuit to perform an OR operation of a normal access signal indicating that now is in the normal access mode and a high-speed access signal indicating that now is in the high-speed access mode, which are outputted by the arithmetic processing unit, and output a result of the OR operation to the bus control unit;
a first logic circuit to input a read signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal;
a second logic circuit to input a write signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal;
an address coincidence determining circuit provided in the arithmetic unit to output a write enable signal from the arithmetic unit when a predetermined address for a memory of the bus control unit coincides with an address designated by the arithmetic processing unit; and
a third logic circuit to input the write enable signal to the bus control unit only when the arithmetic processing unit asserts the high-speed access signal.

Assignees

• Mitsubishi Electric Corp
• Mistubishi Electric Corp

Inventors

• Hoshikawa Masaru
• Watahiki Masataka
• Takenaka Yuta

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• G05B2219/35561

  Analog to digital · CPC title

• G06F13/122 Primary

  where hardware performs an I/O function other than control of data transfer · CPC title