Memory device capable of quickly repairing fail cell

Patent metadata

Field	Value
Publication number	US-10235258-B2
Application number	US-201514683705-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Sep 12, 2014
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

First claim

The invention claimed is:

1. A memory device, comprising: a volatile memory array having a first region configured to store data, a second region configured to store a first portion of fail cell information in memory cells accessed by a second portion of the fail cell memory, and a third region configured to store recovery information, the fail cell information identifying failed cells in the first region, the recovery information for recovering data stored in the identified failed cells, the first portion indicating fail cell column address information of the identified fail cells, the second portion indicating row addresses of the identified fail cells; and a control logic configured to store the fail cell information, to transfer only the first portion of the fail cell information to the second region of the volatile memory array, to determine whether to perform a recovery operation based on address information in an access request and the first portion of the fail cell information stored in the second region, and the access request being a request to access the first region; and a recovery circuit configured to perform a recovery operation in response to the control logic determining to perform the recovery operation.

2. The memory device of claim 1 , wherein the control logic is configured to access the fail cell column address information from the second region using a row address in the address information in the access request.

3. The memory device of claim 2 , wherein the fail cell column address information further includes flag information, the flag information indicating whether the row address accesses one of the identified failed cells.

4. The memory device of claim 2 , wherein the fail cell column address information further includes flag information, the flag information indicating whether the row address accesses one of the identified failed cells.

5. The memory device of claim 1 , wherein the fail cell column address information further includes order information, the order information indicating which data associated with the column addresses is associated with the identified failed cells.

6. The memory device of claim 5 , wherein the fail cell column address information further includes flag information, the flag information indicating whether the fail cell column address information is valid.

7. The memory device of claim 6 , wherein the fail cell column address information further includes parity information, the parity information for correcting errors in the fail cell column address information.

8. The memory device of claim 6 , wherein the fail cell column address information further includes recovery mode information respectively indicating which one of at least two recovery operations to perform for each of the column addresses.

9. The memory device of claim 1 , wherein the fail cell column address information further includes flag information, the flag information indicating which column addresses are valid.

10. The memory device of claim 1 , wherein the fail cell column address information further includes parity information, the parity information for correcting errors in the fail cell column address information.

11. The memory device of claim 10 , wherein the recovery circuit is configured to error correct the column addresses based on the parity information.

12. The memory device of claim 1 , wherein the fail cell column address information further includes recovery mode information respectively indicating which one of at least two recovery operations to perform for each of the column addresses.

13. The memory device of claim 1 , wherein the second region is divided into a plurality of blocks, and the control logic is configured to transfer the fail cell column address information to the second region such that at least two of the plurality of blocks collectively store the fail cell column address information for one of the identified failed cells.

14. The memory device of claim 1 , wherein
the first region is divided into a plurality of first blocks;
the second region is divided into a plurality of second blocks;
each of the plurality of second blocks shares a data line with a respective one of the plurality of first blocks.

15. The memory device of claim 1 , wherein the access request is a write request, and the recovery circuit is configured to obtain the recovery information based on data to be written in response to the control logic determining to perform the recovery operation, and the memory device is configured to store the recovery information in the third region as part of the recovery operation.

16. The memory device of claim 15 , wherein the recovery operation is an error correction operation and the recovery information includes parity bits.

17. The memory device of claim 15 , wherein the recovery operation is a data replacement operation and the recovery information includes data to use as a replacement for the data in the identified failed cells.

18. The memory device of claim 1 , wherein the access request is a read request, and the memory device is configured to read the recovery information in response to the control logic determining to perform the recovery operation, and the recovery circuit is configured to perform the recovery operation based on the read recovery information.

19. The memory device of claim 18 , wherein the recovery operation is an error correction operation and the recovery information includes parity bits.

20. The memory device of claim 19 , wherein the recovery circuit includes an error correction coding circuit configured to error correct code data output at a same time across a plurality of data lines.

21. The memory device of claim 18 , wherein the recovery operation is a data replacement operation and the recovery information includes data to use as a replacement for the data in the identified failed cells.

22. The memory device of claim 1 , wherein the recovery operation is an error correction operation and the recovery information includes parity bits.

23. The memory device of claim 1 , wherein the recovery operation is a data replacement operation and the recovery information includes data to use as a replacement for the data in the failed cell.

24. The memory device of claim 23 , wherein the recovery circuit includes a replacement circuit configured to replace a data line associated with the first region with a data line associated with the third region.

25. The memory device of claim 23 , wherein the recovery circuit includes a replacement circuit configured to replace a bit line associated with the first region with a bit line associated with the third region.

26. The memory device of claim 1 , wherein
the recovery circuit is configured to perform an error correction operation as the recovery operation such that the recovery information includes parity bits, and the recovery circuit is configured to perform a data replacement operation as the recovery operation such that the recovery information includes data to use as a replacement for the data in the failed cell; and
the control logic is configured to control the recovery circuit to perform one of the error correction operation and the data replacement operation as the recovery operation for each column address based on mode information associated with each of the column addresses.

27. A memory device, comprising: a volatile memory array; a control logic

Assignees

• Son Jong Pil
• Park Chul Woo
• Kim Su A
• Samsung Electronics Co Ltd

Inventors

• Son Jong-Pil
• Park Chul-Woo
• Kim Su-A

Classifications

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/4401

  for self repair · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0409

  Online test · CPC title