Booting a system-on-a-chip device

Patent metadata

Field	Value
Publication number	US-10235183-B2
Application number	US-201515519861-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jan 29, 2015
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

Example implementations relate to booting a system comprising a system-on-a-chip (SOC) device. For example, boot code and system code comprising at least one selected from among an operating system and hypervisor code are stored in an on-chip non-volatile memory of a SoC device. By executing the boot code from the on-chip non-volatile memory, the system is booted from a mode in which power is removed from the system, where the booting includes loading the system code in the SoC device from the on-chip non-volatile memory without accessing storage off the SoC device.

First claim

What is claimed is:

1. A method comprising:
storing, in an on-chip non-volatile memory of a system-on-a-chip (SoC) device, boot code and system code comprising at least one selected from among an operating system and hypervisor code;
booting, by executing the boot code from the on-chip non-volatile memory, a system comprising the SoC device from a mode in which power is removed from the system, the booting comprising loading the system code in the SoC device from the on-chip non-volatile memory without accessing storage that is off the SoC device; and
executing in place the boot code and the system code in the on-chip non-volatile memory.

2. The method of claim 1 , wherein loading the operating system comprises loading a kernel and other logic of the operating system.

3. The method of claim 1 , further comprising:
storing a file system in the on-chip non-volatile memory.

4. The method of claim 1 , wherein the on-chip non-volatile memory includes a plurality of logical regions comprising a persistent region, a read-only memory region, and a transient region, the read-only memory region comprising a first portion of the boot code, and the persistent region comprising the system code and a second portion of the boot code, the method further comprising:
accessing metadata in the on-chip non-volatile memory to locate the plurality of logical regions.

5. The method of claim 4 , further comprising:
discarding data in the transient region of the on-chip non-volatile memory in response to a boot of the system.

6. The method of claim 4 , further comprising:
enforcing, using hardware logic of the SoC device, different policies relating to respective logical regions of the plurality of logical regions.

7. A method comprising:
storing, in an on-chip non-volatile memory of a system-on-a-chip (SoC) device, boot code and system code comprising at least one selected from among an operating system and hypervisor code;
booting, by executing the boot code from the on-chip non-volatile memory, a system comprising the SoC device from a mode in which power is removed from the system, the booting comprising loading the system code in the SoC device from the on-chip non-volatile memory without accessing storage that is off the SoC device; and
reading metadata stored in the on-chip non-volatile memory to determine whether to boot or resume the system,
wherein the booting is performed in response to the metadata indicating that the system is to be booted.

8. The method of claim 7 , wherein the on-chip non-volatile memory includes a plurality of logical regions comprising a persistent region and at least one of a read-only memory region and a transient region, the read-only memory region comprising a first portion of the boot code, and the persistent region comprising the system code and a second portion of the boot code, the method further comprising:
accessing the metadata in the on-chip non-volatile memory to locate the plurality of logical regions.

9. The method of claim 8 , further comprising:
discarding data in the transient region of the on-chip non-volatile memory in response to a boot of the system.

10. A system-on-a-chip (SoC) device comprising:
a processor; and
a non-volatile memory including a plurality of regions, at least a first region of the plurality of regions to store boot code and system code comprising at least one selected from among an operating system and hypervisor code, and the plurality of regions further comprising a transient region to store data that is discarded in response to a boot of the SoC device; and
the boot code executable on the processor to boot a system comprising the SoC device from a mode in which power is removed from the system, the booting comprising loading the system code from the non-volatile memory without accessing storage that is off the SoC device, wherein the boot code comprises a first stage bootloader and a second stage bootloader, and wherein the plurality of regions comprise a read-only memory (ROM) region to store the first stage bootloader, and a persistent region to store the second stage bootloader that is invocable by the first stage bootloader, the persistent region to further store the system code.

11. The SoC device of claim 10 , wherein the loading of the system code comprises loading of the operating system that comprises a kernel and additional logic.

12. The SoC device of claim 10 , further comprising a one-time programmable memory to store information that initially allows a write to a given region of the plurality of regions in the non-volatile memory, and after the information in the one-time programmable memory is changed, a further write to the given region is prevented.

13. The SoC device of claim 10 , wherein the non-volatile memory is to store metadata, and the processor is to access the metadata in the non-volatile memory to locate the plurality of regions.

14. The SoC device of claim 10 , further comprising hardware to enforce different policies relating to respective regions of the plurality of regions in the non-volatile memory.

15. A system-on-a-chip (SoC) device comprising:
a processor; and
a non-volatile memory including a plurality of regions, at least a first region of the plurality of regions to store boot code and system code comprising hypervisor code, and the plurality of regions further comprising a transient region to store data that is discarded in response to a boot of the SoC device; and
the boot code executable on the processor to boot a system comprising the SoC device from a mode in which power is removed from the system, the booting comprising loading the system code from the non-volatile memory without accessing storage that is off the SoC device, wherein the loading of the system code comprises loading of the hypervisor code that upon execution causes virtualization of hardware resources of the system.

16. The SoC device of claim 15 , wherein the boot code comprises a first stage bootloader and a second stage bootloader, and wherein the plurality of regions comprise a second region to store the first stage bootloader, and the first region is to store the second stage bootloader that is invocable by the first stage bootloader.

17. The SoC device of claim 15 , wherein the non-volatile memory is to store metadata, and the processor is to access the metadata in the non-volatile memory to locate the plurality of regions in the non-volatile memory.

18. A system comprising:
peripheral devices; and
a system-on-a-chip (SoC) device comprising:
a processor; and
a non-volatile memory including a plurality of regions, at least a first region of the plurality of regions to store a first boot code, a second boot code, and system code comprising at least one selected from among an operating system and hypervisor code, the non-volatile memory to further store metadata relating to the plurality of regions; and
the processor to, as part of booting the system from a mode in which power is removed from the system:
execute the first boot code, the first boot code executable on the processor to find the second boot code using the metadata;
execute the second boot code, the second boot code executable on the processor to find the system code and to load the system code without accessing storage that is off the SoC device; and
execute the system code.

19. The system of claim 18 , wherein the plurality of regions comprise a transient region to store data associated with a volatile main memory, wherein presence of the transient region allows omission of t

Assignees

• Hewlett Packard Development Co

Inventors

• Costa Carlos Haas
• Perez Taciano Dreckmann
• Silva Thiago

Classifications

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4406 Primary

  Loading of operating system · CPC title