Method and apparatus for video encoding and/or decoding to prevent start code confusion

US10230989B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10230989-B2
Application numberUS-201213529446-A
CountryUS
Kind codeB2
Filing dateJun 21, 2012
Priority dateJun 21, 2011
Publication dateMar 12, 2019
Grant dateMar 12, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-transitory computer readable medium comprising instructions that, when executed, cause a video processor to: perform emulation prevention byte insertion on slice data associated with a slice header; perform emulation prevention byte insertion on the slice header after performance of the emulation prevention byte insertion on the slice data; and combine the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 2. The non-transitory computer readable medium of claim 1 , wherein the instructions that cause the video processor to perform emulation prevention byte insertion on the slice data include instructions that cause the video processor to perform emulation prevention byte insertion on the slice data independently from performing emulation prevention byte insertion on the slice header. 3. The non-transitory computer readable medium of claim 1 , wherein the instructions that cause the video processor to perform emulation prevention byte insertion on the slice data include instructions that cause the video processor to perform emulation prevention byte insertion on the slice data without using the slice header. 4. The non-transitory computer readable medium of claim 1 , wherein the instructions further cause the video processor to perform emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data. 5. The non-transitory computer readable medium of claim 1 , wherein the instructions further cause the video processor to insert data at the end of the slice header before the slice data only when the slice header ends with zeros. 6. The non-transitory computer readable medium of claim 5 , wherein the inserted data is ‘FF’. 7. A method comprising: performing, with one or more processors, emulation prevention byte insertion on slice data associated with a slice header; performing, with the one or more processors, emulation prevention byte insertion on the slice header after performance of the emulation prevention byte insertion on the slice data; and combining, with the one or more processors, the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 8. The method of claim 7 , wherein performing the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice data independently from performing emulation prevention byte insertion on the slice header. 9. The method of claim 7 , wherein performing the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice data without using the slice header. 10. The method of claim 7 , wherein performing the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data. 11. The method of claim 7 , wherein the instructions further cause the video processor to insert data at the end of the slice header before the slice data only when the slice header ends with zeros. 12. The method of claim 11 , wherein the inserted data is ‘FF’. 13. A device comprising one or more processors configured to: perform emulation prevention byte insertion on slice data associated with a slice header; perform emulation prevention byte insertion on the slice header after performance of the emulation prevention byte insertion on the slice data; and combine the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 14. The device of claim 13 , wherein performing the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice data without using the slice header. 15. The device of claim 13 , wherein performing the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data. 16. A non-transitory computer readable medium comprising instructions that, when executed, cause a video processor to: perform emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data, perform emulation prevention byte insertion on the slice header in parallel with or after performance of the emulation prevention byte insertion on the slice data; and combine the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 17. The non-transitory computer readable medium of claim 16 , wherein the instructions that cause the video processor to perform emulation prevention byte insertion on the slice header in parallel with or after performance of the emulation prevention byte insertion on the slice data include instructions that cause the video processor to perform emulation prevention byte insertion on the slice header in parallel with performance of the emulation prevention byte insertion on the slice data. 18. A method comprising: performing, with one or more processors, emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data; performing, with the one or more processors, emulation prevention byte insertion on the slice header in parallel with or after performance of the emulation prevention byte insertion on the slice data; and combining, with the one or more processors, the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 19. The method of claim 18 , wherein performing the emulation prevention byte insertion on the slice header in parallel with or after performance of the emulation prevention byte insertion on the slice data includes performing emulation prevention byte insertion on the slice header in parallel with performance of the emulation prevention byte insertion on the slice data. 20. A device comprising one or more processors configured to: perform emulation prevention byte insertion on the slice data while at least one of Sample Adaptive Offset (SAO) and Adaptive Loop Filter (ALF) processes are taking place to generate at least one of SAO and ALF parameters for the slice header associated with the slice data; perform emulation prevention byte insertion on the slice header in parallel with or after performance of the emulation prevention byte insertion on the slice data; and combine the slice header and the slice data after performing the emulation prevention byte insertion on the slice header. 21. The device of claim 20 , wherein performing the emulation preventio

Assignees

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Classifications

  • H04N19/70Primary

    characterised by syntax aspects related to video coding, e.g. related to compression standards · CPC title

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What does patent US10230989B2 cover?
A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slic…
Who is the assignee on this patent?
Sze Vivienne, Budagavi Madhukar, Osamoto Akira, and 2 more
What technology area does this patent fall under?
Primary CPC classification H04N19/70. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).