Forward error control coding

Patent metadata

Field	Value
Publication number	US-10230404-B2
Application number	US-201414580622-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The output RS blocks are then turbo coded. The size of the output RS blocks is selected to match the input of the turbo encoder. The bits from the RS blocks may be interleaved to create the input turbo blocks. Cyclic Redundancy Check (CRC) parity bits may be added to the data prior to RS coding.

First claim

What is claimed is:

1. A transmitter circuit configured to provide forward error correction, the transmitter circuit comprising:
a Cyclic Redundancy Check (CRC) parity bit generator that appends CRC bits to each incoming data block of a set of incoming data;
a Reed-Solomon (RS) coder that creates RS blocks from the incoming data and the CRC bits;
an interleaver that interleaves symbols in the RS blocks to create turbo input blocks; and
a turbo encoder that uses the turbo input blocks to create a signal to be sent to a receiver, wherein the length of the CRC bits appended to each incoming data block is based at least partially upon the turbo input block size.

2. The transmitter circuit of claim 1 , wherein there are M turbo blocks of length L bits and N RS blocks per turbo coder input block such that each RS block has an output size (K) of K=L/8N symbols, wherein output symbols of the RS blocks are arranged in a matrix of size MN×K, wherein each row of the matrix contains output symbols of a corresponding RS block, and wherein the interleaver is further configured to convert the matrix into a symbol vector by raster scanning column wise, and wherein the interleaver is configured to convert the symbol vector into a bit vector by expanding each symbol to 8 bits to generate a long vector of length LM bits.

3. The transmitter circuit of claim 2 , wherein the interleaver is configured to convert the long vector into a matrix of size L×M with each column corresponding to an input turbo block of size L bits.

4. The transmitter circuit of claim 1 , wherein the size of the RS blocks is selected to match the input block size of the turbo coder so that an integer number of RS blocks are interleaved to create the turbo coder input blocks.

5. The transmitter circuit of claim 1 , wherein the interleaver sequentially fills the turbo input blocks with symbols from successive RS blocks.

6. The transmitter circuit of claim 1 , wherein the CRC parity bit generator and the turbo encoder operate using parameters defined in a Long Term Evolution (LTE) standard.

7. A method for encoding data to provide forward error correction, the method comprising:
using a processor of a data transmitter system to:
append Cyclic Redundancy Check (CRC) parity bits to each incoming data block of a set of incoming data;
create Reed-Solomon (RS) encoded blocks from the incoming data and the CRC bits;
interleave symbols in the RS blocks to create turbo input blocks;
turbo encode the turbo input blocks to create a signal to be sent to a receiver, wherein the length of the CRC bits appended to each incoming data block is based at least partially upon the turbo input block size; and
cause the signal to be transmitted to the receiver.

8. The method of claim 7 , wherein there are M turbo blocks of length L bits and N RS blocks per turbo input block such that each RS block has an output size (K) of K=L/8N symbols, wherein output symbols of the RS blocks are arranged in a matrix of size MN×K, wherein each row of the matrix contains output symbols of a corresponding RS block, and wherein interleaving further comprises: converting the matrix into a symbol vector by raster scanning column wise; and converting the symbol vector into a bit vector by expanding each symbol to 8 bits to generate a long vector of length LM bits.

9. The method of claim 8 , wherein interleaving further comprises converting the long vector into a matrix of size L×M with each column corresponding to an input turbo block of size L bits.

10. The method of claim 7 , wherein the size of the RS blocks is selected to match the input block size of the turbo coder so that an integer number of RS blocks are interleaved to create the turbo coder input blocs so that an integer number of RS blocks are interleaved to create the turbo coder input blocks.

11. The method of claim 7 , wherein the interleaving sequentially fills the turbo input blocks with symbols from successive RS blocks.

12. The method of claim 7 , wherein the CRC parity bits are generated and the turbo encoder operates using parameters defined in a Long Term Evolution (LTE) standard.

13. A receiver circuit configured to decode forward error corrected signals, the receiver circuit comprising:
a turbo decoder that decodes received signals to create turbo output blocks;
a de-interleaver that de-interleaves the turbo output blocks to create Reed-Solomon (RS) input blocks;
a Reed-Solomon decoder that receives the RS input blocks and generates decoded output data; and
a Cyclic Redundancy Check (CRC) parity bit check circuit that evaluates CRC bits in the decoded output data, wherein the length of the CRC bits in the decoded output data is based at least partially upon the turbo output block size.

14. The receiver circuit of claim 13 , further comprising:
a Digital Signal Processor (DSP) that provides hardware for the turbo decoder and CRC parity bit check circuit.

15. The receiver circuit of claim 14 , further comprising:
software instructions running on the DSP to provide the RS decoder and the de-interleaver.

16. The receiver circuit of claim 13 , wherein the size of the RS blocks is selected to match the output block size of the turbo decoder so that an integer number of RS blocks are de-interleaved from the turbo decoder output blocks.

17. A method for decoding forward error corrected signals, the method comprising:
receiving, by a data receiver system, signals in a transmission; and
using a processor of the data receiver system to:
turbo decode the received signals to create turbo output blocks;
de-interleave the turbo output blocks to create Reed-Solomon (RS) input blocks;
Reed-Solomon decode the RS input blocks to generate decoded output data; and
evaluate Cyclic Redundancy Check (CRC) parity bits in the decoded output data, wherein the length of the CRC bits in the decoded output data is based at least partially upon the turbo output block size.

18. The method of claim 17 , further comprising:
turbo decoding the received signals and evaluating CRC parity bits and using Digital Signal Processor (DSP) hardware.

19. The method of claim 18 , further comprising:
executing software instructions on the DSP to decode the RS input blocks and to de-interleave the turbo output blocks.

20. The method of claim 17 , wherein the size of the RS blocks is selected to match the output block size of the turbo decoder so that an integer number of RS blocks are de-interleaved from the turbo decoder output blocks.

Assignees

• Texas Instruments Inc

Inventors

• Mansour Mohamed Farouk
• Roh June Chul
• Hosur Srinath

Classifications

• H03M13/27 Primary

  using interleaving techniques · CPC title

• H03M13/618

  Shortening and extension of codes · CPC title

• H03M13/2966

  Turbo codes concatenated with another code, e.g. an outer block code · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title