Memory controller for a non-volatile memory, memory system and method

Patent metadata

Field	Value
Publication number	US-10230401-B2
Application number	US-201715456994-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	Mar 10, 2015
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimension is different from that of the first component code; determine whether the first rewriting process is erroneous correction based on a result of the second decoding process; and when it is determined that the first rewriting process is erroneous correction, perform a counter process which is undoing the first rewriting process based on the recorded first recurrence information.

First claim

What is claimed is:

1. A memory controller that controls a nonvolatile memory in which a multi-dimensional error correction code having two or more component codes is stored, the memory controller comprising:
a memory interface that reads out the multi-dimensional error correction code;
a receiving unit configured to acquire a received word of the multi-dimensional error correction code;
an intermediate decoded word memory that holds an intermediate decoded word of the multi-dimensional error correction code;
a decoder configured to perform a decoding process and detect information relating to an error symbol;
a recurrence information holding unit configured to hold recurrence information for reproducing the information relating to the error symbol detected by the decoding process; and
a control unit configured to
instruct the decoder to perform a first decoding process of a first component code included in the intermediate decoded word,
when a first error symbol included in the first component code is detected by the first decoding process,
perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and
record first recurrence information for reproducing a value of the first error symbol before rewriting in the recurrence information holding unit,

instruct the decoder to perform a second decoding process of a second component code included in the intermediate decoded word, of which a dimension is different from that of the first component code,
determine whether the first rewriting process is an erroneous correction based on a result of the second decoding process, and
when it is determined that the first rewriting process is an erroneous correction, perform a counter process which is undoing the first rewriting process based on the first recurrence information recorded in the recurrence information holding unit.

2. The memory controller according to claim 1 , wherein
the error correction code includes a plurality of first component codes and a plurality of second component codes,
each of the first component codes is generated based on first data including a plurality of pieces of second data,
each of the second component codes is generated based on third data including a plurality of pieces of the second data each of which is singly selected from each of the plurality of pieces of the first data included in fourth data which includes a plurality of pieces of the first data, and
second data included in one third data does not overlap with second data included in another third data.

3. The memory controller according to claim 1 , wherein the second decoding process is performed after the first decoding process.

4. The memory controller according to claim 1 , wherein the decoding process is a bounded distance decoding process.

5. The memory controller according to claim 1 , wherein the first recurrence information is input data to the decoder.

6. The memory controller according to claim 5 , wherein the input data to the decoder is a syndrome value of the first component code.

7. The memory controller according to claim 1 , wherein the recurrence information is information relating to the error symbol detected by the decoding process.

8. The memory controller according to claim 1 , wherein there are one or more of the error symbols detected as being present in the first component code by the first decoding process,
there are one or more of the second component codes that protect respectively the one or more error symbols, and
the control unit decides not to perform the counter process, when at least one of decision criteria is satisfied, of a first decision criterion such that number of the first error symbols detected for the first component code is equal to or greater than a first predetermined number, and a second decision criterion such that number of second component codes that have not succeeded in the decoding process, of the one or more second component codes that protect respectively the one or more error symbols, is equal to or greater than a second predetermined number.

9. The memory controller according to claim 1 , wherein the controller decides not to perform the counter process, when number of iterations of the decoding process by the decoder is equal to or greater than a predetermined number.

10. The memory controller according to claim 1 , wherein at least one of the component codes forming the multi-dimensional error correction code is either a BCH code or an RS (Reed-Solomon) code.

11. The memory controller according to claim 1 , wherein the intermediate decoded word memory holds a symbol value of the respective component codes forming the multi-dimensional error correction code, as the intermediate decoded word.

12. The memory controller according to claim 1 , wherein the intermediate decoded word memory holds a difference between the received word of the multi-dimensional error correction code and the intermediate decoded word, instead of the intermediate decoded word.

13. A memory system comprising:
the memory controller according to claim 1 ; and
a nonvolatile memory that stores the multi-dimensional error correction code.

14. A method of controlling a nonvolatile memory in which a multi-dimensional error correction code having two or more component codes is stored, the method comprising:
reading out the multi-dimensional error correction code;
acquiring a received word of the multi-dimensional error correction code;
holding an intermediate decoded word of the multi-dimensional error correction code;
performing a first decoding process which is decoding a first component code included in the intermediate decoded word;
when one or more first error symbols included in the first component code are detected by the first decoding process,
performing a first rewriting process which is rewriting one or more values corresponding to the one or more first error symbols in the intermediate decoded word, and
recording first recurrence information for reproducing one or more values of the one or more first error symbols before rewriting;

performing a second decoding process which is decoding a second component code included in the intermediate decoded word, of which a dimension is different from that of the first component code;
determining whether the first rewriting process is an erroneous correction based on a result of the second decoding process; and
when it is determined that the first rewriting process is an erroneous correction, performing a counter process which is undoing the first rewriting process based on the recorded first recurrence information.

15. The method according to claim 14 , wherein
the error correction code includes a plurality of first component codes and a plurality of second component codes,
each of the first component codes is generated based on first data including a plurality of pieces of second data,
each of the second component codes is generated based on third data including a plurality of pieces of the second data each of which is singly selected from each of the plurality of pieces of the first data included in fourth data which includes a plurality of pieces of the first data, and
second data included in one third data does not overlap with second data included in another third data.

16. The method according to claim 14 , wherein at least one of the first and second decoding processes includes a bounded distance decoding process.

17. The method according to claim 14 , wherein the first recurrence information is

Assignees

• Toshiba Memory Corp

Inventors

• Watanabe Daiki
• Fujiwara Daisuke
• Morinaga Kosuke
• Torii Osamu

Classifications

• G11C2029/0411

  Online error correction · CPC title

• H03M13/2909 Primary

  Product codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/2927

  Decoding strategies · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title