Variable resolution digital equalization

Patent metadata

Field	Value
Publication number	US-10230384-B2
Application number	US-201715818434-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Dec 9, 2016
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an interface to be coupled to receive a signal that is conveyed via a signal channel, the signal channel to attenuate the signal by an attenuation amount as the signal is conveyed by the signal channel;
an adjustable resolution analog-to-digital converter (ADC) to receive the signal via the interface;
adjustable resolution feed-forward equalization circuitry that amplifies high frequency signal content and noise content to receive, from the ADC, a first digital number representing the received signal and to produce a second digital number based at least in part on a digital finite impulse response filtering of a plurality of digital numbers previously received from the ADC; and,
control circuitry to determine a resolution of the ADC based on the attenuation amount and to determine a resolution of the feed-forward equalization circuitry based on the attenuation amount.

2. The integrated circuit of claim 1 , wherein the ADC corresponds to a successive approximation type ADC.

3. The integrated circuit of claim 2 , wherein the control circuitry determines the resolution of the ADC by controlling the number of successive approximation iterations the ADC uses to convert the received signal to a digital number.

4. The integrated circuit of claim 1 , wherein the control circuitry determines the resolution of the ADC by adjusting the number of comparisons the ADC uses to convert the received signal to a digital number.

5. The integrated circuit of claim 1 , wherein the ADC corresponds to a flash type ADC.

6. The integrated circuit of claim 1 , wherein the resolution of the feed-forward equalization is based at least in part on a required feed-forward equalization gain.

7. The integrated circuit of claim 6 , wherein the control circuitry also determines, based on the attenuation amount, a number of taps that are used to implement the digital finite impulse response filtering.

8. An integrated circuit to receive a signal from a channel that attenuates a transmitted signal by an attenuation factor, comprising:
an adjustable resolution analog-to-digital converter (ADC) to convert the signal from an analog parameter to a first variable resolution digital value;
adjustable resolution feed-forward equalization circuitry that amplifies high frequency signal content and noise content to receive the first variable resolution digital value and to produce a second variable resolution digital value based at least in part on a digital finite impulse response filtering of a time series comprised of a plurality of digital numbers previously received from the ADC; and,
control circuitry to determine a first number of valid bits in the variable resolution digital value based on the attenuation factor and to determine a second resolution of the second variable resolution value based on the attenuation factor.

9. The integrated circuit of claim 8 , wherein the first number of valid bits in the variable resolution digital value is controlled by setting a number of successive approximation iterations performed by the adjustable resolution ADC.

10. The integrated circuit of claim 8 , wherein the first number of valid bits in the variable resolution digital value is controlled by setting a number of active quantization paths used by the adjustable resolution ADC.

11. The integrated circuit of claim 8 , wherein the first number of valid bits in the variable resolution digital value is controlled by activating circuitry to be used by the adjustable resolution ADC.

12. The integrated circuit of claim 8 , wherein portions of circuitry used to implement the digital finite impulse response filtering are activated based at least in part of the first number of valid bits in the variable resolution digital value.

13. The integrated circuit of claim 8 , wherein portions of circuitry used to implement the digital finite impulse response filtering comprise FFE taps that are activated based on the first number of valid bits in the variable resolution digital value.

14. The integrated circuit of claim 8 wherein the adjustable resolution ADC comprises a plurality of ADC converters.

15. A method of producing a digital representation of a signal attenuated by a channel, comprising:
receiving an indicator of an attenuation associated with the channel;
based on the indicator, selecting an output resolution for an analog-to-digital converter (ADC) that receives the signal attenuated by the channel; and,
based on the indicator, selecting a processing resolution for adjustable resolution feed-forward equalization circuitry that amplifies high frequency signal content and noise content and that receives first variable resolution digital values and produces a second variable resolution digital values based at least in part on a digital finite impulse response filtering of a time series comprised of a plurality of digital numbers previously received from the ADC.

16. The method of claim 15 , wherein the output resolution of the analog-to-digital converter depends upon a number of iterations performed by the ADC when converting the signal to a digital number.

17. The method of claim 16 , wherein the number of iterations performed by the ADC when converting the signal to a digital number is based on the indicator meeting a first threshold criteria.

18. The method of claim 15 , wherein the output resolution of the analog-to-digital converter depends upon a number of comparators used by the ADC when converting the signal to a digital number.

19. The method of claim 18 , wherein a number of comparators used by the ADC when converting the signal to a digital number is based on the indicator meeting a first threshold criteria.

20. The method of claim 15 , further comprising:
selecting, based on the indicator, a number of taps used for the digital finite impulse response filtering of a series of digital numbers from the ADC.

Assignees

• Rambus Inc

Inventors

• Hossain Masum
• Dyer Kenneth C
• Nguyen Nhat
• Tangirala Shankar

Classifications

• H03M1/365

  the voltage divider being a single resistor string · CPC title

• H04L25/03

  Shaping networks in transmitter or receiver, e.g. adaptive shaping networks · CPC title

• H04L25/03038

  with a non-recursive structure (H04L25/03031 takes precedence) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title