Phase shifter

Patent metadata

Field	Value
Publication number	US-10230378-B2
Application number	US-201816021143-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jul 7, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

First claim

The invention claimed is:

1. A phase shifter circuit having an active state and an inactive state, the phase shifter circuit comprising:
a digital-to-analogue converter configured to receive a control signal indicative of a desired phase shift and to provide an analogue current in accordance with the desired phase shift;
a mixer stage configured to mix an oscillator signal with the analogue current to provide a phase shifted signal; and
control circuitry configured to provide the oscillator signal to the mixer stage in accordance with the state of the phase shifter to activate or deactivate the mixer stage.

2. The phase shifter circuit of claim 1 , wherein the control circuitry is configured to receive a raw oscillator signal and to supply an adjusted oscillator signal to the mixer stage in accordance with the state of the phase shifter.

3. The phase shifter circuit of claim 1 , wherein the control circuitry comprises a switchable bias voltage source and is configured to apply a first bias level to the mixer stage in the active state to activate the mixer stage and a different, second bias level to the mixer stage in the inactive state to deactivate the mixer stage.

4. The phase shifter circuit of claim 3 , wherein the second bias level is a ground level.

5. The phase shifter circuit of claim 3 , wherein the mixer stage and digital-to-analogue converter are arranged such that application of the second bias level to the mixer stage reduces a potential difference between an output of the digital-to-analogue converter at which the analogue current is provided and ground.

6. The phase shifter circuit of claim 3 , wherein the control circuitry comprises a balun with a first inductor and a second inductor, wherein the first inductor is configured to receive an unbalanced oscillator signal, wherein the second inductor is configured to provide a balanced signal to a mixer of the mixer stage in accordance with the bias applied by the switchable bias voltage of the control circuitry.

7. The phase shifter circuit of claim 1 , wherein the digital-to-analogue converter, DAC, is a current-summing converter with a plurality of units, the phase shifter circuit further comprising a DAC bias voltage source and a filter configured to provide a DAC bias voltage to each of the units of the digital-to-analogue converter.

8. The phase shifter circuit of claim 7 , wherein the DAC bias voltage source is configured to provide the DAC bias voltage to the digital-to-analogue converter in both the active state and the inactive state.

9. The phase shifter circuit of claim 7 , wherein each unit comprises a first DAC switch, a second DAC switch and a field effect transistor with a gate connected to the DAC bias voltage and a conduction channel connected to the first and second DAC switches.

10. The phase shifter circuit of claim 9 , wherein:
the mixer comprises first, second, third and fourth transistors, the first and second transistors each having a first junction coupled to the first DAC switches for receiving a current, the third and fourth transistors each having a first junction coupled to the second DAC switches for receiving a current, the second and fourth transistors each having second junctions for providing an output of the mixer, the first and third transistors each having second junctions for providing a second output of the mixer, the second and third transistors each having a control terminal for receiving a first balanced oscillator signal, and the first and fourth transistors each having a control terminal for receiving a second balanced oscillator signal.

11. The phase shifter circuit of claim 1 , wherein the mixer stage comprises an in-phase mixer, a quadrature mixer and a power combiner configured to combine output signals from the in-phase and quadrature mixers.

12. A transmitter module having a ramp-up state and a ramp-down state, the transmitter module comprising:
a digital-to-analogue converter configured to receive a control signal indicative of a desired phase shift and to provide an analogue current in accordance with the desired Phase shift;
a mixer stage configured to mix an oscillator signal with the analogue current to provide a phase shifted signal;
control circuitry configured to provide the oscillator signal to the mixer stage in accordance with the state of the phase shifter to activate or deactivate the mixer stage; and
a controller configured to send a control signal to the control circuitry of the phase shifter circuit to set a state of the phase shifter circuit in accordance with the state of the transmitter.

13. The transmitter module of claim 12 , wherein the transmitter module is a radar transmitter module.

14. A method of shifting a phase of an oscillator signal, comprising:
receiving a digital control signal indicative of a desired phase shift;
providing by way of a digital-to-analogue converter, DAC, an analogue current in accordance with the desired phase shift;
setting by way of control circuitry an oscillator signal in accordance with an active state or an inactive state; and
mixing the oscillator signal with the analogue current by way of a mixer stage to provide a phase shifted signal.

15. A computer program configured to enable a processor to perform the method of claim 14 .

16. The method of claim 14 , further comprising receiving a raw oscillator signal at the control circuitry and supplying an adjusted oscillator signal to the mixer stage in accordance with the active state or the inactive state.

17. The method of claim 14 , further comprising applying a first bias level to the mixer stage in the active state to activate the mixer stage and applying a second bias level to the mixer stage in the inactive state to deactivate the mixer stage, the second bias level different from the first bias level.

18. The method of claim 17 , wherein the control circuitry comprises a balun with a first inductor and a second inductor, wherein the first inductor is configured to receive an unbalanced oscillator signal, and wherein the second inductor is configured to provide a balanced signal to a mixer of the mixer stage.

19. The method of claim 14 , wherein the DAC is a current-summing converter with a plurality of units, and further comprising providing a DAC bias voltage to each of the units of the DAC.

20. The method of claim 14 , wherein the mixer stage comprises an in-phase mixer, a quadrature mixer and a power combiner configured to combine output signals from the in-phase and quadrature mixers.

Assignees

• Nxp Bv

Inventors

• Thuries Stephane
• Pavao Moreira Cristian
• Montoriol Gilles

Classifications

• H04B1/44

  Transmit/receive switching · CPC title

• H03M1/665

  with intermediate conversion to phase of sinusoidal or similar periodical signals · CPC title

• G01S13/288

  phase modulated · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• G01S13/70

  for range tracking only · CPC title