Vertical-transport transistors with self-aligned contacts

Patent metadata

Field	Value
Publication number	US-10230000-B2
Application number	US-201715671605-A
Country	US
Kind code	B2
Filing date	Aug 8, 2017
Priority date	Aug 8, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

First claim

What is claimed is:

1. A method of forming a vertical-transport field-effect transistor, the method comprising:
forming a semiconductor fin that projects from a first source/drain region;
epitaxially growing a second source/drain region that is spaced vertically along the semiconductor fin from the first source/drain region;
forming a gate stack arranged between the second source/drain region and the first source/drain region;
forming a first spacer adjacent to a first sidewall of the second source/drain region;
forming a second spacer adjacent to a second sidewall of the second source/drain region;
after forming the first spacer and the second spacer, recessing a top surface of the second source/drain region;
forming a dielectric cap on the top surface of the second source/drain region;
forming a first contact extending through the dielectric cap and connected with a top surface of the second source/drain region;
forming a second contact connected with a top surface of the first source/drain region; and
forming a third contact connected with a top surface of the gate stack,
wherein the first spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

2. The method of claim 1 wherein the first spacer and the second spacer are concurrently formed.

3. The method of claim 1 wherein forming the dielectric cap comprises:
depositing a dielectric material in a space above the top surface of the second source/drain region that is interior of the first spacer and the second spacer to form the dielectric cap.

4. The method of claim 1 wherein the first spacer is arranged between the second source/drain region and the second contact, and the second contact is in direct contact with the first spacer.

5. The method of claim 1 wherein the first spacer is arranged between the second source/drain region and the third contact, and the third contact is in direct contact with the first spacer.

6. A method of forming a vertical-transport field-effect transistor, the method comprising:
forming a semiconductor fin that projects from a first source/drain region;
epitaxially growing a second source/drain region that is spaced vertically along the semiconductor fin from the first source/drain region;
forming a gate stack arranged between the second source/drain region and the first source/drain region;
recessing a top surface of the second source/drain region;
forming a dielectric cap on the top surface of the second source/drain region;
after the dielectric cap is formed, forming a first spacer adjacent to a first sidewall of the second source/drain region;
forming a first contact connected with a top surface of the second source/drain region;
forming a second contact connected with a top surface of the first source/drain region; and
forming a third contact connected with a top surface of the gate stack,
wherein the first spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

7. The method of claim 1 wherein the second source/drain region is formed in a dielectric layer, and forming the first spacer adjacent to the first sidewall of the second source/drain region comprises:
recessing the dielectric layer to reveal the first sidewall of the second source/drain region.

8. The method of claim 6 wherein the first spacer is arranged between the second source/drain region and the second contact, and further comprising:
forming a second spacer adjacent to a second sidewall of the second source/drain region,
wherein the second spacer is arranged between the second source/drain region and the third contact.

9. The method of claim 6 wherein the first spacer is arranged between the second source/drain region and the third contact, and further comprising:
forming a second spacer adjacent to a second sidewall of the second source/drain region,
wherein the second spacer is arranged between the second source/drain region and the second contact.

10. The method of claim 6 wherein the first spacer is arranged between the second source/drain region and the second contact, and the second contact is in direct contact with the first spacer.

11. The method of claim 6 wherein the first spacer is arranged between the second source/drain region and the third contact, and the third contact is in direct contact with the first spacer.

12. The method of claim 6 wherein the second source/drain region is formed in a dielectric layer, and forming the first spacer adjacent to the first sidewall of the second source/drain region comprises:
recessing the dielectric layer to reveal the first sidewall of the second source/drain region.

13. The method of claim 6 wherein forming the first contact connected with the top surface of the second source/drain region further comprises:
before forming the first contact, completely removing the dielectric cap from the top surface of the second source/drain region,
wherein the first contact includes a first portion that directly contacts an entirety of the top surface of the second source/drain region.

14. The method of claim 8 wherein the first spacer and the second spacer are concurrently formed.

15. The method of claim 8 wherein forming the dielectric cap comprises:
depositing a dielectric material in a space above the top surface of the second source/drain region that is interior of the first spacer and the second spacer to form the dielectric cap.

16. The method of claim 9 wherein the first spacer and the second spacer are concurrently formed.

17. The method of claim 13 further comprising:
narrowing a second portion of the first contact that is arranged over the first portion of the first contact; and
forming a second spacer arranged adjacent to the second portion of the first contact and over the first portion of the first contact.

18. The method of claim 17 wherein the second spacer is arranged between the first contact and the second contact after the second contact is formed, and the first contact and the second contact are in direct contact with the second spacer.

19. The method of claim 17 wherein the second spacer is arranged between the first contact and the third contact after the third contact is formed, and the first contact and the third contact are in direct contact with the second spacer.

Assignees

• Globalfoundries Inc

Inventors

• Bourjot Emilie
• Chanemougame Daniel
• Lee Tek Po Rinus
• Xie Ruilong
• Zang Hui

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/78618 Primary

  Electricity · mapped topic