Flash memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10229926-B2
Application number	US-201815926791-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 22, 2017
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A method for manufacturing a flash memory device includes providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer. The method also includes performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer, and forming an isolation region on side surfaces of the stack structure. The method can mitigate the problem of an undesirable increase in the threshold voltage with an increase in the integration density of the flash memory device.

First claim

What is claimed is:

1. A method for manufacturing a flash memory device, comprising:
providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer;
performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer; and
forming an isolation region on side surfaces of the stack structure.

2. The method of claim 1 , wherein performing the selective nitriding process comprises an energy of nitrogen in a range between 1.5 eV and 3.0 eV.

3. The method of claim 2 , wherein the energy of nitrogen is in a range between 1.5 eV and 2.0 eV.

4. The method of claim 1 , wherein performing the selective nitriding process comprises a nitrogen dose in a range between 1×10 15 atoms/cm 2 and 1×10 16 atoms/cm 2 .

5. The method of claim 1 , wherein performing the selective nitriding process comprises a pressure in a range between 0.1 torr and 10 torr.

6. The method of claim 1 , wherein forming the isolation region comprises:
forming a repair oxide layer on the side surfaces of the stack structure;
forming an isolation material layer on the repair oxide layer.

7. The method of claim 6 , further comprising, prior to forming the isolation material layer on the repair oxide layer:
forming a barrier oxide layer on the repair oxide layer, and the isolation material layer being formed on the barrier oxide layer.

8. The method of claim 6 , wherein forming the repair oxide layer comprises a rapid thermal oxidation process.

9. The method of claim 6 , wherein forming the isolation material layer comprises a rapid thermal oxidation process, a furnace oxidation process, a chemical vapor deposition process, or an atomic layer deposition process.

10. The method of claim 1 , wherein providing the substrate structure comprises:
providing the substrate;
forming the insulating layer on the substrate;
forming the charge storage layer on the insulating layer;
forming the tunneling dielectric layer on the charge storage layer;
forming the charge trapping layer on the tunneling dielectric layer;
forming the blocking dielectric layer on the charge trapping layer; and
forming the gate layer on the blocking dielectric layer.

11. The method of claim 1 , wherein:
the tunneling dielectric layer comprises silicon oxide;
the charge trapping layer comprises silicon nitride; or
the blocking dielectric layer comprises silicon oxide; or
the charge storage layer and the gate layer each comprise polysilicon.

12. A flash memory device, comprising:
a substrate;
an insulating layer on the substrate;
a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer;
an isolation region on side surfaces of the stack structure; and
a nitride layer disposed between a portion of the isolation region and the charge storage layer and between a portion of the isolation region and the gate layer.

13. The flash memory device of claim 12 , wherein the isolation region comprises:
a repair oxide layer on a side surface of the stack structure; and
an insulating material layer on the repair oxide layer.

14. The flash memory device of claim 13 , wherein the isolation region further comprises:
a barrier oxide layer between the repair oxide layer and the insulating material layer.

15. The flash memory device of claim 12 , wherein:
the tunneling dielectric layer comprises silicon oxide;
the charge trapping layer comprises silicon nitride; or
the blocking dielectric layer comprises silicon oxide; or
the charge storage layer and the gate layer each comprise polysilicon.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Yu Guobin
• Xu Xiaoping

Classifications

• H01L21/8239

  Electricity · mapped topic

• H01L27/115

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L27/11568 Primary

  Electricity · mapped topic

• H10D64/037

  comprising charge-trapping insulators · CPC title