Chip arrangement and method for checking whether a chip is arranged in an intended chip carrier

Patent metadata

Field	Value
Publication number	US-10229352-B2
Application number	US-201414549578-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 22, 2013
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

One embodiment describes a chip arrangement having a chip carrier; a chip which is arranged in or on the chip carrier; a light sensor arrangement; a transparent layer which covers the light sensor arrangement, the light sensor arrangement being set up to determine a light pattern of light received by the light sensor arrangement from outside the chip arrangement through the transparent layer; and a test circuit which is set up to check whether the light pattern matches a reference light pattern and to output a signal on the basis of the result of the check.

First claim

What is claimed is:

1. A chip arrangement, comprising:
a chip carrier;
a chip which is arranged in or on the chip carrier;
a light sensor arrangement, arranged on the chip, in the chip or beside the chip;
a transparent layer which covers the light sensor arrangement; and wherein the transparent layer comprises an optical pattern;
wherein the light sensor arrangement is configured to determine a light pattern of light received by the light sensor arrangement from outside the chip arrangement through the transparent layer; wherein the light pattern of light is projected onto the light sensor arrangement by an external chip reader;
a test circuit, connected to the light sensor arrangement, and configured to check whether the light pattern matches a reference light pattern and to output a signal on the basis of the result of the check.

2. The chip arrangement of claim 1 ,
wherein the chip arrangement is a chip card; and
wherein the chip carrier is a chip card body.

3. The chip arrangement of claim 1 ,
wherein the chip arrangement is an identification document;
wherein the chip is an identification chip; and
wherein the chip carrier is a carrier material of the identification document.

4. The chip arrangement of claim 1 ,
wherein the light sensor arrangement is arranged on the chip.

5. The chip arrangement of claim 1 ,
wherein the chip comprises the light sensor arrangement.

6. The chip arrangement of claim 1 ,
wherein the chip comprises the test circuit.

7. The chip arrangement of claim 1 ,
wherein the transparent layer is a film.

8. The chip arrangement of claim 1 ,
wherein the transparent layer comprises the optical pattern comprising transparent and opaque elements.

9. The chip arrangement of claim 1 ,
wherein the optical pattern comprises elements which are opaque or transparent depending on a frequency or wavelength of light.

10. The chip arrangement of claim 1 ,
wherein the transparent layer is arranged on the light sensor arrangement, which is arranged in the chip carrier.

11. The chip arrangement of claim 1 ,
wherein the test circuit is configured to output the signal to a checking apparatus which is outside the chip arrangement.

12. The chip arrangement of claim 1 , further comprising:
a memory configured to store information relating to the reference light pattern;
wherein the test circuit is configured to check whether the light pattern matches the reference light pattern on the basis of the information relating to the reference light pattern.

13. The chip arrangement of claim 12 ,
wherein the information relating to the reference light pattern is a hash value of the reference light pattern.

14. The chip arrangement of claim 1 ,
wherein the light sensor arrangement comprises a plurality of light sensors.

Assignees

• Infineon Technologies Ag

Inventors

• Klimke Martin
• Gammel Berndt
• Pueschner Frank
• Stampka Peter

Classifications

• G06K19/077

  Constructional details, e.g. mounting of circuits in the carrier · CPC title

• G06K19/06009

  with optically detectable marking (G06K19/063, G06K19/08 take precedence) · CPC title

• G06K19/07381 Primary

  with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering · CPC title