Computing in parallel processing environments

Patent metadata

Field	Value
Publication number	US-10229083-B1
Application number	US-201715693863-A
Country	US
Kind code	B1
Filing date	Sep 1, 2017
Priority date	Mar 5, 2014
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

First claim

What is claimed is:

1. A method for multi-processor communication among plural nodes of a multi-processor, the method comprising:
performing by a sender node of the plural nodes, (sender node) a fetch and add operation;
remapping the fetch and add operation to an associated conditional atomic operation;
sending the associated conditional atomic operation to a receiver node of the plural nodes, (receiver node) over a fabric transport of the multi-processor; and
atomically converting by the receiver node the associated conditional atomic operation to a FetchAddGEZ operation.

2. The method of claim 1 , further comprising:
coordinating by the sender node and the receiver node on a set of FetchAddGEZ memory locations to be used for FIFO controls.

3. The method of claim 1 , further comprising:
reading by the receiver node a current memory location from the coordinated set of memory locations used for the FIFO controls;
adding by the receiver node a value from the fetch and add operation to the value from the current memory location; and
testing by the receiver node a value resulting from the adding operation.

4. The method of claim 2 , wherein if the result from the adding operation is greater than or equal to zero, the result is committed to memory and otherwise, the memory is left intact and the original memory contents are returned to the sender.

5. The method of claim 2 wherein the fabric transport is PCI Express or Ethernet.

6. The method of claim 5 wherein the fabric transport is PCI Express and serialization hardware in the PCI Express fabric transport conditionally performs the conditional atomic operation.

7. The method of claim 2 , further comprises:
providing the FetchAddGEZ operation as a layered service; and
deploying a shared FIFO for communication between the sender and the receiver nodes over the fabric.

8. A method for multi-processor communication among plural nodes of a multi-processor using shared FIFOs, the method comprising:
performing by a sender node of the plural nodes, (sender node) a FetchAndAdd operation to provide a value;
remapping by the sender node, the FetchAndAdd operation to an associated conditional atomic operation on a fabric transport; and
sending the associated conditional atomic operation to a receiver node of the plural nodes, (receiver node) over a fabric transport for conversion to an operation.

9. The method of claim 8 , further comprising:
coordinating by the sender node with the receiver node, to determine a set of memory locations to be used for FIFO controls of the shared FIFOs.

10. The method of claim 9 wherein the associated atomic operation is converted to a FetchAddGEZ operation and the set of memory locations are locations storing values from the FetchAddGEZ operation.

11. The method of claim 5 wherein the conditional atomic operation allows serialization hardware to conditionally perform the operation based on current memory contents.

12. The method of claim 5 wherein the associated atomic operation is converted to a FetchAddGEZ operation.

13. The method of claim 12 wherein the FetchAddGEZ operation is an operation that fetches a current value, adds a value to the current value, and tests if a result is greater than or equal to zero.

14. A method for multi-processor communication among plural nodes of a multi-processor using shared FIFOs and a FetchAndAdd operation, the method comprising:
reading by a receiver node of the plural nodes, (receiver node) a current memory location determined from a coordinated set of memory locations that are used for FIFO controls;
adding by the receiver node a value resulting from a FetchAndAdd operation to a value read from the current memory location; and
testing by the receiver node a value resulting from the adding operation.

15. The method of claim 14 wherein if the value resulting from the adding operation is greater than or equal to zero, the resulting value is committed to memory.

16. The method of claim 14 wherein if the value resulting from the adding operation is not greater than or equal to zero, the current memory location is left intact and the original memory contents are returned to the sender.

17. A computing system comprising:
a tiled multicore processor that includes plural processor tiles, with the processor tiles comprising a processor, memory, and a switch;
a fabric coupling the plurality of tiles; and the tiled multicore processor configurable to:
communicate using shared FIFOs over the fabric;
perform by a sender tile of the plural processor tiles (sender tile) a fetch and add operation;
remap the fetch add operation to an associated conditional atomic operation;
send the associated conditional atomic operation to a receiver tile of the plural processor tiles (receiver tile) over the fabric; and
atomically convert by the receiver node the remapped operation to a FetchAddGEZ operation.

18. The system of claim 17 wherein the tiled multi-processor is further configurable to:
coordinate on a set of FetchAddGEZ memory locations to be used for FIFO controls by the sender tile and the receiver tile.

19. The system of claim 17 wherein the tiled multi-processor is further configurable to:
read by the receiver node a current memory location from the coordinated set of memory locations used for the FIFO controls;
add by the receiver tile the value from the fetch and add operation to the value from the current memory location; and
test by the receiver tile the value resulting from the adding operation.

20. The system of claim 17 wherein if the result from the adding operation is greater than or equal to zero, the result is committed to memory and otherwise, the memory is left intact and the original memory contents are returned to the sender tile.

21. The system of claim 17 wherein the fabric transport is PCI Express or Ethernet.

22. The system of claim 17 wherein the fabric transport is PCI Express, and serialization hardware in the PCI Express fabric transport conditionally performs the conditional atomic operation.

23. The system of claim 17 wherein the FetchAddGEZ operation is a layered service and system further comprises:
a shared FIFO for communication between the sender tile and the receiver tile over the fabric using the FetchAddGEZ operation as a layered service.

Assignees

• Ramey Carl G
• Mellanox Technologies Ltd

Inventors

• Ramey Carl G

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title