Method for data transfer between real-time tasks using a DMA memory controller

Patent metadata

Field	Value
Publication number	US-10229077-B2
Application number	US-201515125942-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 25, 2014
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

The invention is directed a method for transferring at least one datum between a real-time task producing a datum and a real-time task consuming said datum. The method may include, in response to initiation of a transfer of a datum by a current instance of an initiating task: creating at least one DMA descriptor describing the DMA transfer expected for said datum; inserting DMA descriptors into a list of descriptors awaiting processing by a DMA controller, said DMA descriptors being inserted in a manner sorted based on a sorting criterion relating to a visibility date of the data and/or a temporal behavior of the tasks; processing the descriptors on the list of DMA descriptors by executing DMA requests; and executing the following instance of the initiating task based on termination of the processing a predefined set of DMA descriptors on the list of descriptors.

First claim

The invention claimed is:

1. A method for transferring at least one datum between a real-time task producing a datum and a real-time task consuming said datum, each datum being associated with a visibility date, said method being implemented in a computer comprising a central memory, at least one processor and at least one direct memory access DMA controller, each DMA controller being configured to handle data transfers between various areas of the central memory under the control of an operating system that is executed on said processors, wherein the method comprises the following steps, in response to initiation of the transfer of a datum by the current instance of an initiating task:
creating, by the operating system, of at least one DMA descriptor for describing the DMA transfer expected for said datum, after execution of a given instance of the task;
inserting, by said operating system, of the DMA descriptors into a list of descriptors awaiting processing by said DMA controller, said DMA descriptors being inserted in a sorted manner based on a sorting criterion relating to the visibility date of the data and/or on the temporal behavior of the tasks;
processing the descriptors on said list of DMA descriptors by executing DMA requests via the DMA controller; and
executing of the following instance of the initiating task by the operating system based on the termination of the processing a predefined set of the DMA descriptors of said list of descriptors.

2. The method as claimed in claim 1 , comprising a step of verifying, by the operating system, of the termination of the processing said predefined set of the DMA descriptors of said list.

3. The method as claimed in claim 1 , wherein initiating includes producing data, and wherein creating the DMA descriptors is triggered in response to termination of the execution of the current instance of the initiating task.

4. The method as claimed in claim 3 , wherein said sorting criterion is the visibility date associated with the datum to be transferred.

5. The method as claimed in claim 2 , wherein said set of descriptors comprises DMA descriptors that have a visibility date less than or equal to the activation date of the next instance of the initiating task, and wherein the verification step is implemented by determining whether the descriptors in said set are associated with end of processing information.

6. The method as claimed in claim 1 , wherein the initiating task is a data consuming task, and wherein the step of creation of the DMA descriptors is triggered in response to termination of the execution of the preceding instance of the initiating task.

7. The method as claimed in claim 6 , wherein the sorting criterion is the expiry date of the current instance of the initiating task.

8. The method as claimed in claim 6 , wherein said set of descriptors comprises the set of DMA descriptors that were created in the creation step, and wherein the verification step is implemented by determining whether the descriptors in said set are associated with end of processing information.

9. The method as claimed in claim 1 , wherein said insertion step moreover comprises temporary suspension of DMA requests being executed by the DMA controller, said suspension time being used by the operating system to update the list of DMA descriptors.

10. The method as claimed in claim 2 , comprising a termination step in which the status bits of the DMA descriptors processed in the execution step by the DMA controller are set to indicate the end of processing of the DMA descriptors.

11. The method as claimed in claim 1 , comprising notifying, by the DMA controller, the operating system of the end of data transfers within the central memory, wherein the operating system is capable of storing end of transfer information in a data structure in the form of a list of terminated data transfers.

12. The method as claimed in claim 2 , wherein the verification step on a datum is delayed until the first instant of use by the task of the memory area storing the datum.

13. The method as claimed in claim 1 , wherein the computer comprises at least one hardware memory protection mechanism associated with the DMA controller in order to safeguard data transfers by programming via hardware registers that are accessible by said processor, said method comprising:
in the step of insertion of the DMA descriptors, programming of the hardware registers with the memory rights that are necessary for performing transfer of said datum; or
on detection of an invalid access by the hardware memory protection mechanism, verification that the corresponding memory access belongs to one of the DMA descriptors created in the creation step for transfer of said datum and programming of the registers of the memory protection hardware with the memory rights that are necessary for performing transfer of said datum.

14. The method as claimed in claim 1 , wherein the computer comprises at least one hardware memory protection mechanism associated with the DMA controller in order to safeguard transfers of a datum and using memory descriptors with which it is provided by means of extensions in the format of a DMA descriptor in order to include the description of the authorized memory rights for the DMA requests associated with the DMA descriptor, said memory rights being used in the execution step via the DMA controller in order to program the hardware memory protection mechanism with the memory rights that are necessary so as to perform transfer of said datum.

15. A computer comprising a central memory, at least one processor and at least one direct memory access DMA controller, each DMA controller being configured to handle data transfers between various areas of the central memory under the control of an operating system that is executed on said processors, the computer being configured to transfer at least one datum between a real-time task producing a datum and a real-time task consuming said datum, each datum being associated with a visibility date, wherein, in response to initiation of transfer of a datum by the current instance of an initiating task: the operating system is capable of creating at least one DMA descriptor in order to describe the DMA transfer expected for said datum, after execution of a given instance of the task, and to insert DMA descriptors into a list of descriptors awaiting processing by said DMA controller, said DMA descriptors being inserted in a manner sorted based on a sorting criterion relating to the visibility date of the data and/or to the temporal behavior of the tasks; the DMA controller is configured to process the descriptors in said list of DMA descriptors by executing DMA requests; and wherein the operating system is moreover configured to execute the following instance of the initiating task based on termination of the processing of a predefined set of the DMA descriptors of said list of descriptors.

Assignees

• Commissariat Energie Atomique

Inventors

• Jan Mathieu
• Debicki Olivier

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title