Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages

Patent metadata

Field	Value
Publication number	US-10229076-B2
Application number	US-201514848929-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Sep 9, 2015
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

First claim

What is claimed is:

1. A Peripheral Component Interconnect Express (PCIe) communication system, comprising:
a first device configured to:
determine at least one memory write information to be sent to a second device via a PCIe link;
encode the memory write information as a vendor defined message (VDM), wherein a header of the VDM is encoded based on a format of a direct memory access (DMA) header, wherein encoding the header of the VDM comprises encoding one or more fields of the header of the VDM with values that correspond to one or more fields of a DMA header; and
send the VDM to a second device over the PCIe link; and

the second device configured to:
receive the VDM from the first device;
store the VDM in a dedicated buffer, wherein the buffer is dedicated to storing VDMs; and
send the VDMs on a dedicated channel, wherein the dedicated channel is dedicated to sending VDMs.

2. The system of claim 1 , wherein the first device comprises an end point device, and the second device comprises a root complex device.

3. The system of claim 1 , wherein the first device comprises logic for:
receiving a plurality of credits indicating a number of packets allowed for the first device to send to the second device; and
reserving at least one of the plurality of credits for sending the VDM.

4. The system of claim 3 , wherein reserving the credit comprises reserving a last credit of the plurality of credits.

5. The system of claim 1 , wherein the first device is configured to send DMA information to the second device via the PCIe link.

6. The system of claim 1 , wherein the VDM is a transaction layer packet (TLP).

7. The system of claim 1 , wherein encoding the one or more fields of the header of the VDM with values that correspond to one or more fields of the DMA header further comprises:
overloading the one or more fields of the header of the VDM with values that correspond to the one or more fields of the DMA header.

8. The system of claim 7 , wherein overloading the one or more fields of the header of the VDM with values from the one or more fields of the DMA header further comprises:
overloading a tag field of the header of the VDM with values that correspond to the last double-work byte enable (DW BE) and first DW BE fields of the DMA header.

9. The system of claim 7 , wherein overloading the one or more fields of the header of the VDM with values from the one or more fields of the DMA header further comprises:
overloading a reserved bus field, a device number filed, and a function number field of the header of the VDM with values that correspond to a first address field of the DMA header.

10. The system of claim 7 , wherein overloading the one or more fields of the header of the VDM with values from the one or more fields of the DMA header further comprises:
overloading a vendor identification field of the header of the VDM with values that correspond to a second address field of the DMA header.

Assignees

• IBM

Inventors

• Lais Eric N
• Yanes Adalberto G

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/0026

  PCI express · CPC title