Unified hardware and software two-level memory

Patent metadata

Field	Value
Publication number	US-10229065-B2
Application number	US-201615396460-A
Country	US
Kind code	B2
Filing date	Dec 31, 2016
Priority date	Dec 31, 2016
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.

First claim

What is claimed is:

1. A method comprising:
implementing a two-level memory access mechanism for a compute platform installed in one of a first chassis, drawer, tray or sled communicatively coupled, via a fabric, to one of a second chassis, drawer, tray or sled in which one or more far memory devices are installed, the compute platform including a processor operatively coupled to one or more near memory devices and enabled to access the one or more far memory devices via the fabric, wherein an access latency for a near memory device is less than an access latency for a far memory device, at least a portion of memory in the one or more near memory devices storing data in data units having addresses in a near memory virtual address space and at least a portion of memory in the one or more far memory devices storing data in data units having addresses in a far memory virtual address space;
executing a plurality of processes on the processor;
assigning levels of service to at least a portion of the plurality of processes;
storing data in data units having addresses in the near memory virtual address space and in data units having addresses in the far memory virtual address space, a portion of the data that is stored being stored in data units in both the near memory virtual address space and the far memory virtual address space;
in response to a memory read access request including a virtual memory address corresponding to a data unit storing data to be accessed,
determining whether the data is stored in a near memory device, and, if so,
accessing the data from the near memory device; otherwise,
accessing the data from a far memory device via the fabric;

monitoring access patterns to data in the far memory virtual address space;
based on the access patterns, copying data units from the far memory virtual address space into the near memory virtual address space; and
determining, at least in part, whether to copy data units from the far memory virtual address space into the near memory virtual address space based on a level of service assigned to a process that requests access to data that is not stored in the near memory virtual address space.

2. The method of claim 1 , further comprising mapping, for each data unit in the near memory virtual address space, an address of the data unit in the near memory virtual address space to an address of the data unit in the far memory virtual address space.

3. The method of claim 1 , wherein the near memory devices are volatile memory devices and the far memory devices are non-volatile memory devices.

4. The method of claim 3 , wherein the non-volatile memory devices include three-dimensional crosspoint memory devices.

5. The method of claim 1 , further comprising accessing a far memory device over the fabric using a Non-volatile Memory Express over Fabric (NVMe-oF) protocol.

6. The method of claim 5 , wherein the far memory device comprises a storage class memory device.

7. The method of claim 1 , wherein the data units comprise memory pages.

8. The method of claim 1 , wherein the one or more far memory devices comprise one or more block storage devices, and the data units comprise storage blocks.

9. A system, comprising:
a compute platform including a processor having a memory controller;
one or more near memory devices, communicatively coupled to the memory controller;
a host fabric interface (HFI), communicatively coupled to the processor and communicatively coupled to a fabric including a plurality of fabric links and at least one fabric switch; and
one or more far memory devices, communicatively coupled to the fabric;
wherein an access latency for a near memory device is less than an access latency for a far memory device, at least a portion of the memory in the one or more near memory devices configured to store data in data units having addresses in a near memory virtual address space and at least a portion of the memory in the one or more far memory devices configured to store data in data units having addresses in a far memory virtual address space, and wherein the system is configured to,
execute a plurality of processes on the processor;
assign levels of service to at least a portion of the plurality of processes;
store data in data units having addresses in the near memory virtual address space and in data units having addresses in the far memory virtual address space, a portion of the data that is stored being stored in data units in both the near memory virtual address space and the far memory virtual address space;
in response to a memory read access request including a virtual memory address corresponding to a data unit storing data to be accessed,
determine whether the data is stored in a near memory device, and, if so,
access the data from the near memory device; otherwise,
access the data from a far memory device via the fabric;

monitor access patterns to data in the far memory virtual address space;
based on the access patterns, copy data units from the far memory virtual address space into the near memory virtual address space
determine, at least in part, whether to copy data units from the far memory virtual address space into the near memory virtual address space based on a level of service assigned to a process that requests access to data that is not stored in the near memory virtual address space.

10. The system of claim 9 , wherein the system is further configured to map, for each data unit in the near memory virtual address space, an address of the data unit in the near memory virtual address space to an address of the data unit in the far memory virtual address space.

11. The system of claim 9 , wherein the near memory devices are volatile memory devices and the far memory devices are non-volatile memory devices.

12. The system of claim 11 , wherein the non-volatile memory devices include three-dimensional crosspoint memory devices.

13. The system of claim 9 , wherein the system is further configured to access the one or more far memory devices over the fabric using a Non-volatile Memory Express over Fabric (NVMe-oF) protocol.

14. The system of claim 9 , wherein the data units comprise memory pages.

15. The system of claim 9 , wherein the one or more far memory devices comprise one or more block storage devices, and the data units comprise storage blocks.

16. A non-transient machine readable medium having instructions stored thereon, configured to be executed on a processor in a compute platform including one or more near memory devices and one or more far memory devices operatively coupled to the processor, wherein an access latency for a near memory device is less than an access latency for a far memory device, at least a portion of the memory in the one or more near memory devices storing data in data units having addresses in a near memory virtual address space and at least a portion of the memory in the one or more far memory devices storing data in data units having addresses in a far memory virtual address space, wherein the compute platform is configured to execute a plurality of processes on the processor, at least a portion of the processes having an associated level of service, and wherein the instructions, when executed enable the compute platform to:
store data in data units having addresses in the near memory virtual address space and in data units having addresses in the far memory virtual address space, a portion of the data that is stored being stored in data units in both the near memory virtual address space and the far memory virtual address space;
in response to a memory read access req

Assignees

• Intel Corp

Inventors

• Kumar Mohan J
• Nachimuthu Murugasamy K

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/154

  Networked environment · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F3/067 Primary

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F3/0629 Primary

  Configuration or reconfiguration of storage systems · CPC title