Programmable matrix processing engine

Patent metadata

Field	Value
Publication number	US-10228937-B2
Application number	US-201615395654-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

An apparatus may comprise a multi-dimensional memory, a plurality of matrix processors, and a matrix routine memory. The matrix routine memory may store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processors. Further, the plurality of matrix processors may be configured to: receive a command to perform a matrix operation; receive matrix data from the multi-dimensional memory; extract one or more matrix operands from the matrix data; identify a programmable matrix routine associated with the matrix operation; receive the programmable matrix routine from the matrix routine memory; execute the programmable matrix routine using the one or more matrix operands; and obtain a result of the matrix operation based on execution of the programmable matrix routine.

First claim

What is claimed is:

1. An apparatus, comprising:
a multi-dimensional memory;
a plurality of matrix processors;
a matrix routine memory to store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processors;
wherein the plurality of matrix processors is configured to:
receive a command to perform a matrix operation;
receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with one or more matrix operands for the matrix operation;
extract the one or more matrix operands from the matrix data;
identify a programmable matrix routine associated with the matrix operation, wherein the programmable matrix routine is identified from the plurality of programmable matrix routines;
receive the programmable matrix routine from the matrix routine memory;
execute the programmable matrix routine using the one or more matrix operands; and
obtain a result of the matrix operation based on execution of the programmable matrix routine.

2. The apparatus of claim 1 , wherein the plurality of matrix processors is further configured to:
receive the programmable matrix routine from a host computing system; and
store the programmable matrix routine in the matrix routine memory.

3. The apparatus of claim 1 , wherein the programmable matrix routine comprises a first plurality of instructions associated with the matrix operation.

4. The apparatus of claim 3 , wherein the first plurality of instructions comprises an indication of one or more memory locations associated with the one or more matrix operands.

5. The apparatus of claim 1 , wherein the plurality of matrix processors to extract the one or more matrix operands from the matrix data is further configured to slice the matrix data to extract the one or more matrix operands.

6. The apparatus of claim 1 , wherein the plurality of matrix processors is further configured to execute one or more instructions to extract the one or more matrix operands from the matrix data.

7. The apparatus of claim 1 , wherein the plurality of matrix processors is further configured to execute one or more instructions to obtain the matrix data from one or more memory locations of the multi-dimensional memory.

8. The apparatus of claim 1 , wherein the matrix operation comprises one or more matrix multiplication operations.

9. The apparatus of claim 1 , wherein the matrix operation comprises one or more convolution operations.

10. The apparatus of claim 1 , wherein the matrix operation is associated with an operation in a neural network.

11. A method, comprising:
receiving a command to perform a matrix operation;
receiving matrix data from a multi-dimensional memory, wherein the matrix data is associated with one or more matrix operands for the matrix operation;
extracting one or more matrix operands from the matrix data;
identifying a programmable matrix routine associated with the matrix operation, wherein the programmable matrix routine is identified from a plurality of programmable matrix routines stored on a matrix routine memory, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by a plurality of matrix processors;
receiving the programmable matrix routine from the matrix routine memory;
executing the programmable matrix routine on the plurality of matrix processors using the one or more matrix operands; and
obtaining a result of the matrix operation based on execution of the programmable matrix routine.

12. The method of claim 11 , wherein the programmable matrix routine comprises a first plurality of instructions associated with the matrix operation.

13. The method of claim 12 , wherein the first plurality of instructions comprises an indication of one or more memory locations associated with the one or more matrix operands.

14. A system, comprising:
a plurality of memory elements, wherein the plurality of memory elements comprises a multi-dimensional memory; and
a plurality of processing elements, comprising:
a host processor; and
one or more matrix processing chips;

a matrix routine memory to store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processing chips;
wherein the plurality of processing elements is configured to:
receive a command to perform a matrix operation;
receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with one or more matrix operands for the matrix operation;
extract the one or more matrix operands from the matrix data;
identify a programmable matrix routine associated with the matrix operation, wherein the programmable matrix routine is identified from the plurality of programmable matrix routines;
receive the programmable matrix routine from the matrix routine memory;
execute the programmable matrix routine using the one or more matrix operands; and
obtain a result of the matrix operation based on execution of the programmable matrix routine.

15. The system of claim 14 , wherein each matrix processing chip comprises a plurality of matrix processing clusters.

16. The system of claim 15 , wherein each matrix processing cluster comprises a plurality of matrix processing units.

17. The system of claim 15 , wherein each matrix processing cluster comprises a plurality of memory resource blocks.

18. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to:
receive a command to perform a matrix operation;
receive matrix data from a multi-dimensional memory, wherein the matrix data is associated with one or more matrix operands for the matrix operation;
extract the one or more matrix operands from the matrix data;
identify a programmable matrix routine associated with the matrix operation, wherein the programmable matrix routine is identified from a plurality of programmable matrix routines stored on a matrix routine memory, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by a plurality of matrix processors;
receive the programmable matrix routine from the matrix routine memory;
execute the programmable matrix routine on the plurality of matrix processors using the one or more matrix operands; and
obtain a result of the matrix operation based on execution of the programmable matrix routine.

19. The storage medium of claim 18 , wherein the programmable matrix routine comprises a first plurality of instructions associated with the matrix operation.

20. The storage medium of claim 19 , wherein the first plurality of instructions comprises an indication of one or more memory locations associated with the one or more matrix operands.

21. The storage medium of claim 18 , wherein the instructions that cause the machine to receive the matrix data from the multi-dimensional memory further cause the machine to obtain the matrix data from one or more memory locations of the multi-di

Assignees

• Intel Corp

Inventors

• Werner Tony L
• Kalaiah Aravind
• Korthikanti Vijay
• Lau Horace

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06N3/084

  Backpropagation, e.g. using gradient descent · CPC title

• G06N3/063

  using electronic means · CPC title