Measurement system that stores pre- and post-qualification signal data

Patent metadata

Field	Value
Publication number	US-10228394-B2
Application number	US-201615057023-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Feb 29, 2016
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

First claim

What is claimed is:

1. A measurement system comprising:
an analog-to-digital converter (ADC) configured to sample a time-varying waveform to create an acquisition record made up of acquired digital data samples;
memory; and
a processor configured to perform a qualified store algorithm when the measurement system is in a qualified storage mode of operations, wherein when the processor performs the qualified store algorithm, the processor stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

2. A measurement system that ensures that a preselected number of digital data samples are stored before and after a qualification signal becomes valid when the measurement system is performing a qualified store algorithm, the measurement system comprising:
an analog-to-digital converter (ADC) configured to sample a time-varying waveform to create an acquisition record made up of acquired digital data samples;
memory; and
a processor configured to perform the qualified store algorithm when the measurement system is in a qualified storage mode of operations, wherein when the processor performs the qualified store algorithm, the processor causes N digital data samples acquired before the qualification signal became valid to be stored in a first portion of memory, causes X digital data samples acquired during a time window that starts when the qualification signal becomes valid and ends when the qualification signal becomes invalid to be stored in a second portion of memory, and causes M digital data samples acquired after the qualification signal becomes invalid to be stored in a third portion of memory, where N, X and M are integers.

3. The measurement system of claim 2 , wherein the ADC, the memory and the processor are parts of a data acquisition system of the measurement system.

4. The measurement system of claim 3 , wherein the first portion of memory is configured to operate as a circular buffer having N sample locations for storing the N digital data samples, respectively.

5. The measurement system of claim 4 , wherein the first, second and third portions of memory are respective portions of a single memory device.

6. The measurement system of claim 4 , wherein the second and third portions of memory are respective portions of a single, first memory device and wherein the first portion of memory that operates as a circular buffer is part of a second memory device that is separate from the first memory device.

7. The measurement system of claim 4 , wherein the processor is configured as a finite state machine (FSM) having at least a pre-qualification storage (Store Pre-Qual) state, a qualification storage (Store Qual) state and a post-qualification storage (Store Post-Qual) state, wherein when the FSM is in the Store Pre-Qual state, the processor causes the N digital data samples acquired before the qualification signal became valid to be stored in the first portion of memory, and wherein when the FSM is in the Store Pre-Qual state and the qualification signal becomes valid, the FSM exits the Store Pre-Qual state and enters the Store Qual state, and wherein when the FSM is in the Store Qual state, the processor causes the X digital data samples to be stored in the second portion of memory, and wherein when the FSM is in the Store Qual state and the qualification signal becomes invalid, the FSM exits the Store Qual state and enters the Store Post-Qual state, and wherein when the FSM is in the Store Post-Qual state, the processor causes the M digital data samples to be stored in the third portion of memory.

8. The measurement system of claim 7 , wherein if the FSM is in the Store Post-Qual state and the M digital data samples have been stored in the third portion of memory, the FSM exits the Store Post-Qual state and re-enters the Store Pre-Qual state, and wherein when the FSM re-enters the Store Pre-Qual state, the processor causes N newly-acquired digital data samples to be stored in the first portion of memory.

9. The measurement system of claim 8 , wherein once the FSM has re-entered the Store Pre-Qual state and N newly-acquired digital data samples have been stored in the first portion of memory, if the qualification signal becomes valid, the FSM re-enters the Store Qual state and X newly-acquired digital data samples are stored in the second portion of the memory.

10. The measurement system of claim 9 , wherein once the FSM has re-entered the Store Qual state and X newly-acquired digital data samples have been stored in the second portion of memory, if the qualification signal becomes invalid, the FSM re-enters the Store Post-Qual state and M newly-acquired digital data samples are stored in the third portion of the memory.

11. The measurement system of claim 7 , wherein if the FSM is in the Store Post-Qual state and the qualification signal becomes valid before all of the M digital data samples have been stored in the third portion of memory, the FSM exits the Store Post-Qual state and re-enters the Store Qual state, and wherein when the FSM re-enters the Store Qual state, the processor causes X digital data samples to be stored in the second portion of memory.

12. The measurement system of claim 11 , wherein if the FSM is in the Store Post-Qual state and the qualification signal becomes valid before all of the M digital data samples have been stored in the third portion of memory, the FSM causes a log entry to be stored in a log in memory.

13. The measurement system of claim 8 , wherein if the FSM has re-entered the Store Pre-Qual state after exiting the Store Post-Qual state and the qualification signal becomes valid before the N newly-acquired digital data samples have been stored in the first portion of memory, the FSM exits the Store Pre-Qual state and re-enters the Store Qual state, and wherein when the FSM re-enters the Store Qual state, the processor causes X digital data samples to be stored in the second portion of memory.

14. The measurement system of claim 13 , wherein if the FSM has re-entered the Store Pre-Qual state after exiting the Store Post-Qual state and the qualification signal becomes valid before the N newly-acquired digital data samples have been stored in the first portion of memory, the FSM causes a log entry to be stored in a log in memory.

15. The measurement system of claim 14 , wherein if the FSM has re-entered the Store Pre-Qual state after exiting the Store Post-Qual state and the qualification signal becomes valid before the N newly-acquired digital data samples have been stored in the first portion of memory, the FSM causes a sample index of all digital data samples since the start of data acquisition to be stored in memory.

16. The measurement system of claim 13 , wherein if the FSM has re-entered the Store Pre-Qual state after exiting the Store Post-Qual state and the qualification signal becomes valid before the N newly-acquired digital data samples have been stored in the first portion of memory, the FSM causes a log entry to be stored in a log in memory.

17. The measurement system of claim 2 , wherein each time the qualification signal changes from invalid to valid after a first time that the qualification signal changes from invalid to valid, a finite state machine (FSM) causes a log entry to be stored in a log in memory.

18. The measurement system of claim 17 , wherein eac

Assignees

• Keysight Technologies Inc

Inventors

• Montijo Allen

Classifications

• G11C21/00

  Digital stores in which the information circulates {continuously}(stepwise G11C19/00) · CPC title

• G01R13/029 Primary

  Software therefor · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G01R13/0272

  for sampling · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title