PCB based semiconductor package with impedance matching network elements integrated therein

Patent metadata

Field	Value
Publication number	US-10225922-B2
Application number	US-201615046923-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a metal baseplate having a die attach region and a peripheral region;
a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate; and
a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate, the multilayer circuit board comprising:
a first embedded electrically conductive layer that is separated from the first side by a first layer of composite fiber;
a second embedded electrically conductive layer that is separated from the second side by a second layer of composite fiber; and
an embedded dielectric layer disposed between the first and second embedded electrically conductive layers,

wherein the embedded dielectric layer has a higher dielectric constant than each of the first and second layers of composite fiber.

2. The semiconductor package of claim 1 , wherein the multilayer circuit board comprises:
a first electrically conductive signal layer disposed at the second side;
a first electrically conductive ground layer embedded in the multilayer circuit board;
a second electrically conductive signal layer embedded in the multilayer circuit board;
a second electrically conductive ground layer disposed at the first side, wherein:
the first layer of composite fiber separates the first signal layer from the first ground layer,
the second layer of composite fiber separates the second signal layer from the second ground layer,
the embedded dielectric layer separates the first ground layer from the second signal layer, and
the embedded dielectric layer has a lesser thickness than each of the first and second layers of composite fiber.

3. The semiconductor package of claim 2 , wherein the embedded dielectric layer has a dielectric constant of between 4 and 30, and wherein the first and second composite fiber layers each have a dielectric constant of 3.7 or less.

4. The semiconductor package of claim 3 , wherein the embedded dielectric layer is formed from a polymer laminate material, and wherein the first and second composite fiber layers are formed from at least one of: FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5.

5. The semiconductor package of claim 3 , wherein the embedded dielectric layer has a thickness of between 4 μm and 50 μm, and wherein the first and second composite fiber layers each have a thickness of at least 75 μm.

6. The semiconductor package of claim 2 , wherein the multilayer circuit board comprises:
a first electrically conductive via extending through the first composite fiber layer and connected to a first bonding pad, the first bonding pad being formed by an isolated portion of the first signal layer and; and
one or more embedded reactive components electrically connected to the first via, each of the one or more embedded reactive components comprising an isolated section of the second signal layer.

7. The semiconductor package of claim 6 , wherein the one or more embedded reactive components comprise a first capacitor, wherein a positive electrode of the first capacitor is formed by a first isolated section of the second signal layer, and wherein a ground electrode of the first capacitor is formed by a first isolated section of the first ground layer.

8. The semiconductor package of claim 7 , wherein the first capacitor has a capacitance of at least 100 picoFarads.

9. The semiconductor package of claim 6 , wherein the one or more embedded reactive components comprise:
a shunt inductance connected to the first electrically conductive via and comprising a linear strip of the second signal layer; and
an open-circuit radial stub connected to the shunt inductance and comprising a radially shaped section of the second signal layer.

10. The semiconductor package of claim 9 , further comprising:
a first set of bond wires directly connected between the RF terminal and the first bonding pad.

11. The semiconductor package of claim 10 , further comprising:
a second bonding pad formed by an isolated portion of the first signal layer; and
a second set of bond wires directly connected between the RF terminal and the second bonding pad,
wherein the first set of bond wires extends in a first direction between the RF terminal and the first bonding pad,
wherein the second set of bond wires extends in a second direction between the RF terminal and the second bonding pad, and
wherein the second direction is non-parallel to the first direction.

12. The semiconductor package of claim 6 , further comprising a discrete capacitor formed on or in the baseplate and connected to the one or more embedded reactive components.

13. The semiconductor package of claim 12 , wherein the multilayer circuit board comprises a third bonding pad formed by an isolated portion of the first signal layer, wherein the discrete capacitor is a surface-mount capacitor that is directly mounted on the third bonding pad, and wherein the third bonding pad is electrically connected to the one or more embedded reactive components by a second electrically conductive via extending through the first composite fiber layer.

14. A semiconductor assembly, comprising:
a metal baseplate having a die attach region and a peripheral region;
a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate;
a global printed circuit board; and
a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate, the multilayer circuit board comprising:
a first embedded electrically conductive layer that is separated from the first side by a first layer of composite fiber;
a second embedded electrically conductive layer that is separated from the second side by a second layer of composite fiber; and
an embedded dielectric layer disposed between the first and second embedded electrically conductive layers;
an RF impedance matching network comprising one or more reactive components formed from at least one of the embedded electrically conductive layers,
wherein the embedded dielectric layer has a higher dielectric constant than the first and second layers of composite fiber, and
wherein the multilayer circuit board connects the RF terminal of the transistor die to the global printed circuit board.

15. The semiconductor assembly of claim 14 , wherein the multilayer circuit board comprises:
a first electrically conductive signal layer disposed at the second side;
a first electrically conductive ground layer embedded in the multilayer circuit board;
a second electrically conductive signal layer embedded in the multilayer circuit board;
a second electrically conductive ground layer disposed at the first side, wherein:
the first layer of composite fiber separates the first signal layer from the first ground layer,
the second layer of composite fiber separates the second signal layer from the second ground layer,
the embedded dielectric layer separates the first ground layer from the second signal layer, and
the embedded dielectric layer has a lesser thickness than each of the first and second layers of composite fiber.

16. The semiconductor assembly of claim 15 , wherein the embedded dielectric layer has a dielectric constant of between 4 and 30, wherein the first and second composite fiber layers each have a dielectric constant of 3.7 or less, wherein the embedded dielectric layer has a thickness of between 4 μm and 50 μm, and wherein the f

Assignees

• Infineon Technologies Ag
• Cree Inc

Inventors

• Mu Qianli
• Gozzi Cristian
• Dani Asmita

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title