Data storage control apparatus and data storage control method

Patent metadata

Field	Value
Publication number	US-10225569-B2
Application number	US-201514659828-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 31, 2014
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A compressed data generator compresses, by using a lossless compressor and a lossy compressor, image data in units of first blocks to generate a plurality of types of compressed data. A selector performs selection processing in units of second blocks each including a predetermined number N of first blocks, where N is an integer of 1 or more. The selection processing involves determining whether each of the plurality of types of compressed data satisfies a selection condition and selecting one piece of compressed data that satisfies the selection condition. The selection condition includes a data size condition that a data size of all the first blocks included in the second block is less than or equal to a predetermined value, and a data accuracy condition that information maintaining accuracy is highest among compressed data that satisfy the data size condition.

First claim

What is claimed is:

1. A data storage control apparatus comprising:
compressor circuitry configured to compress image data and outputs compressed data; and
writing controller circuitry configured to write said compressed data as write data to a memory, wherein
said compressor circuitry includes:
compressed data generator circuitry that includes lossless compressor circuitry configured to perform lossless compression and lossy compressor circuitry configured to perform lossy compression, and that is configured to compress, by using said lossless compressor circuitry and said lossy compressor circuitry, said image data in units of first blocks, each being an image block of a predetermined area size, to generate a plurality of types of compressed data in parallel or in series such that the plurality of types of compressed data are generated from each of a single first block; and
selector circuitry configured to perform selection processing on each second block that includes a predetermined number N of said first blocks, where N is an integer of 1 or more, said selection processing involving determining whether each of said plurality of types of compressed data generated by said compressed data generator circuitry satisfies a predetermined selection condition and selecting one piece of compressed data that satisfies said predetermined selection condition,

said predetermined selection condition includes:
a data size condition that a data size of all of said first blocks included in said second block is less than or equal to a predetermined value; and
a data accuracy condition that information maintaining accuracy is highest among said compressed data that satisfies said data size condition,

said writing controller circuitry is configured to write said one piece of compressed data selected by said selector circuitry as said write data to said memory,
said lossless compression is processing for obtaining a difference in pixel value between a compression target pixel and a standard pixel and assigning a resultant difference value to said compression target pixel,
said lossless compressor circuitry is configured to define said compression target pixel and said standard pixel in said first block in accordance with a predetermined pixel classification and perform said lossless compression on said compression target pixel and said standard pixel that have been defined,
said lossy compressor circuitry includes at least one of:
first lossy compression processor circuitry configured to generate first compressed data by performing first low-pass processing using a first low-pass filter on compression target data;
second lossy compression processor circuitry configured to generate second compressed data by performing said first low-pass processing and said lossless compression in this order on said compression target data; and
third lossy compression processor circuitry configured to generate at least one piece of third compressed data by performing said first low-pass processing and said lossless compression in this order on said compression target data and performing a first bit shift processing in which a bit of said difference value obtained from said lossless compression is shifted toward the least significant bit.

2. The data storage control apparatus according to claim 1 , wherein
said predetermined pixel classification includes a first pixel classification according to which pairs of pixels are sequentially selected in said first block, each of pairs including pixels adjacent to each other in said first block that are defined with one pixel as said compression target pixel and the other pixel as said standard pixel.

3. The data storage control apparatus according to claim 1 , wherein
said predetermined pixel classification includes a second pixel classification according to which a pixel at a predetermined fixed position in said first block is defined as said standard pixel, and each pixel at a position other than said fixed position in said first block is defined as said compression target pixel.

4. The data storage control apparatus according to claim 1 , wherein
said at least one piece of third compressed data is a plurality of pieces of third compressed data that are generated by using different shift amounts in said first bit shift processing.

5. The data storage control apparatus according to claim 1 , wherein
said lossy compressor circuitry further includes at least one of:
fourth lossy compression processor circuitry configured to generate fourth compressed data by performing second low-pass processing using a second low-pass filter on said compression target data, said second low-pass filter having a different strength from said first low-pass filter;
fifth lossy compression processor circuitry configured to generate fifth compressed data by sequentially performing said second low-pass processing and said lossless compression on said compression target data; and
sixth lossy compression processor circuitry configured to generate at least one piece of sixth compressed data by performing said second low-pass processing and said lossless compression in this order on said compression target data, and performing a second bit shift processing in which a bit of said difference value obtained from said lossless compression is shifted toward the least significant bit.

6. The data storage control apparatus according to claim 5 , wherein
said at least one piece of sixth compressed data is a plurality of pieces of sixth compressed data that are generated by using different shift amounts in said second bit shift processing.

7. The data storage control apparatus according to claim 1 , wherein
said lossless compressor circuitry and said lossy compressor circuitry operate in parallel.

8. The data storage control apparatus according to claim 1 , further comprising:
an input buffer memory that temporarily stores said image data that is to be supplied to said compressor,
wherein said lossless compression or said lossy compression includes reference-type processing that uses, as a reference object, a first block that is not set to a compression object among said first blocks, and
said input buffer memory stores said image data of a first block that is scheduled to be used as either said compression object or said reference object, and frees a storage area allocated to a first block that is no longer scheduled to be used as either said compression object or said reference object, at a predetermined timing.

9. The data storage control apparatus according to claim 8 , wherein
said compressor acquires said image data in units of third blocks, each including a predetermined number X of said second blocks, where X is an integer of 1 or more, from said input buffer memory, and
said input buffer memory manages said storage area in association with said third blocks.

10. The data storage control apparatus according to claim 8 , further comprising:
an output buffer memory that temporarily stores said write data that is output from said compressor for the supply to said writing controller,
wherein said memory includes a plurality of banks, and
said writing controller writes said write data to said memory while switching said plurality of banks every piece of said write data.

11. The data storage control apparatus according to claim 10 , wherein
said writing controller waits for Y banks' worth of said write data to be accumulated in said output buffer memory, where Y is an integer of 2 or more, and collectively writes said Y banks' worth of said write data to said memory.

12. The data storage control apparatus according to claim 8 , wherein
upstream of said inpu

Assignees

• Megachips Corp

Inventors

• Okamoto Akira
• Madanbashi Tomoaki

Classifications

• H04N19/182

  the unit being a pixel · CPC title

• H04N19/12

  Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264 · CPC title

• H04N19/132

  Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking · CPC title

• H04N19/80

  Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation (H04N19/635, H04N19/86 take precedence) · CPC title

• H04N19/15

  by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer · CPC title