Clock and data recovery circuit having tunable fractional-N phase locked loop

Patent metadata

Field	Value
Publication number	US-10224937-B1
Application number	US-201815959104-A
Country	US
Kind code	B1
Filing date	Apr 20, 2018
Priority date	Apr 20, 2018
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

First claim

What is claimed is:

1. A clock and data recovery (CDR) circuit, comprising:
a phase interpolator;
a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator;
a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, of a sampling clock supplied by the phase interpolator;
a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path; and
a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

2. The CDR circuit of claim 1 , wherein the fractional-N PLL includes a delta-sigma modulator (DSM), and wherein the control input of the fractional-N PLL is coupled to the DSM.

3. The CDR circuit of claim 1 , wherein the frequency path comprises:
a scale circuit coupled to the control input of the fractional-N PLL;
an integrator coupled to the phase detector;
a first multiplexer coupled between the integrator and the phase path;
a second multiplexer coupled between the integrator and the scale circuit.

4. The CDR circuit of claim 3 , wherein the frequency path further comprises:
a gain circuit coupled between the integrator and the phase detector.

5. The CDR circuit of claim 3 , wherein the frequency path further comprises:
a divider coupled between the integrator and the first multiplexer.

6. The CDR circuit of claim 3 , wherein the first multiplexer includes a first port coupled to an output of the integrator and a second port configured to receive a constant ‘0’ signal, and wherein the second multiplexer includes a first port configured to receive the constant ‘0’ signal and a second port coupled to the output of the integrator.

7. The CDR circuit of claim 6 , wherein the control circuit is coupled to control ports of the first and second multiplexers, respectively, to select either the first port or the second port, respectively.

8. A receiver, comprising:
sampling circuitry configured to generate data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock;
a phase interpolator configured to supply the sampling clock in response to a phase interpolator code;
a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator;
a phase detector configured to generate a phase detect result signal in response to the data samples and the crossing samples;
a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path; and
a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

9. The receiver of claim 8 , wherein the fractional-N PLL includes a delta-sigma modulator (DSM), and wherein the control input of the fractional-N PLL is coupled to the DSM.

10. The receiver of claim 8 , wherein the frequency path comprises:
a scale circuit coupled to the control input of the fractional-N PLL;
an integrator coupled to the phase detector;
a first multiplexer coupled between the integrator and the phase path;
a second multiplexer coupled between the integrator and the scale circuit.

11. The receiver of claim 10 , wherein the frequency path further comprises:
a gain circuit coupled between the integrator and the phase detector.

12. The receiver of claim 10 , wherein the frequency path further comprises:
a divider coupled between the integrator and the first multiplexer.

13. The receiver of claim 10 , wherein the first multiplexer includes a first port coupled to an output of the integrator and a second port configured to receive a constant ‘0’ signal, and wherein the second multiplexer includes a first port configured to receive the constant ‘0’ signal and a second port coupled to the output of the integrator.

14. The receiver of claim 13 , wherein the control circuit is coupled to control ports of the first and second multiplexers, respectively, to select either the first port or the second port, respectively.

15. A method of clock and data recovery in a receiver, comprising:
generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver;
supplying a clock signal to the phase interpolator using a fractional-N phase locked loop (PLL);
generating a phase detect result signal in response to phase detection of the data samples and the crossing samples;
filtering the phase detect result signal through digital loop filter having a phase path and a frequency path to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code;
controlling the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

16. The method of claim 15 , wherein the fractional-N PLL includes a delta-sigma modulator (DSM), and wherein the control input of the fractional-N PLL is coupled to the DSM.

17. The method of claim 15 , wherein the frequency path comprises:
a scale circuit coupled to the control input of the fractional-N PLL;
an integrator coupled to the phase detector;
a first multiplexer coupled between the integrator and the phase path;
a second multiplexer coupled between the integrator and the scale circuit.

18. The method of claim 17 , wherein the frequency path further comprises:
a gain circuit coupled between the integrator and the phase detector.

19. The method of claim 17 , wherein the frequency path further comprises:
a divider coupled between the integrator and the first multiplexer.

20. The method of claim 17 , wherein the first multiplexer includes a first port coupled to an output of the integrator and a second port configured to receive a constant ‘0’ signal, and wherein the second multiplexer includes a first port configured to receive the constant ‘0’ signal and a second port coupled to the output of the integrator.

Assignees

• Xilinx Inc

Inventors

• Wu Zhaoyin D
• Zhang Geoffrey
• Upadhyaya Parag
• Chang Kun-Yung

Classifications

• H04L7/0025

  interpolation of clock signal · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title