Closed-loop digital compensation scheme

Patent metadata

Field	Value
Publication number	US-10224877-B2
Application number	US-201715581057-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Jan 20, 2017
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

First claim

What is claimed is:

1. A method for amplifying an audio signal with audio amplifier circuitry, comprising:
receiving a digital input signal;
converting the digital input signal to an analog signal in a digital-to-analog converter (DAC);
producing an output analog signal with an amplifier coupled to the digital-to-analog converter (DAC); and
applying a digital compensation to the digital input signal to compensate for resistor mismatch in resistors of the audio amplifier circuitry, wherein the digital compensation is based, at least in part, on a resistor mismatch and a supply voltage.

2. The method of claim 1 , further comprising monitoring a supply voltage of the amplifier to obtain the supply voltage.

3. The method of claim 1 , further comprising predicting an output duty cycle of the amplifier based, at least in part, on the digital input signal.

4. The method of claim 3 , wherein the step of predicting the output duty cycle is also based, at least in part, on a gain setting of the amplifier and a pulse-width modulation (PWM) modulator ramp amplitude.

5. The method of claim 4 , wherein the step of applying digital compensation to the digital input signal is based, at least in part, on one or more digital output codes corresponding to a gain setting of the amplifier.

6. The method of claim 5 , further comprising generating the one or more digital output codes by performing steps comprising:
powering down a power stage of the amplifier, wherein the power stage is coupled to the analog output node;
driving a load attached to the analog output node from a non-power stage component in an analog domain of the amplifier to a reference voltage different from a common mode voltage of the digital-to-analog converter (DAC), wherein the non-power stage component is coupled to the analog output node through the power stage;
monitoring a differential input to the analog domain by comparing a first input of the differential input with a second input of the differential input;
adjusting a digital compensation applied to the digital input node to identify a digital code that causes the first input to approximately equal the second input; and
storing, in a memory, a digital code corresponding to the digital compensation that causes the first input to cross the second input.

7. The method of claim 6 , wherein the step of adjusting the digital compensation to identify the digital code comprises adjusting the digital compensation until the digital code causes the first input to cross the second input.

8. The method of claim 6 , wherein the step of applying the digital compensation comprises:
retrieving the digital code;
adjusting the digital code based on the supply voltage; and
applying the adjusted digital code to the digital input signal to compensate for resistor mismatch.

9. An audio amplifier circuit, comprising:
a digital-to-analog converter (DAC) coupled to a digital input node and configured to convert a digital input signal to an input analog signal;
an amplifier comprising an analog input node and an analog output node, wherein the amplifier is configured to output to the analog output node an amplified version of the input analog signal received at the analog input node; and
a digital compensation block coupled to the digital input node and configured to apply digital compensation to compensate for resistor mismatch to the digital input signal, wherein the digital compensation is based, at least in part, on a resistor mismatch and a supply voltage.

10. The apparatus of claim 9 , further comprising a supply voltage monitor block configured to determine the supply voltage and coupled to the digital compensation block.

11. The apparatus of claim 9 , wherein the digital compensation block is further configured to predict an output duty cycle at the analog output node, wherein the output duty cycle is based, at least in part, on the digital input signal.

12. The apparatus of claim 11 , wherein the digital compensation block is configured to predict the output duty cycle based, at least in part, on a gain setting of the amplifier and a pulse-width modulation (PWM) modulator ramp amplitude of the amplifier.

13. The apparatus of claim 12 , wherein the digital compensation block is configured to apply a digital code based, at least in part, on one or more digital compensation codes corresponding to the gain setting of the amplifier.

14. The apparatus of claim 13 , wherein the digital compensation block is configured to generate the one or more digital compensation codes by performing steps comprising:
monitoring a differential input to the amplifier by comparing a first input of the differential input with a second input of the differential input;
adjusting the digital code applied to the digital input node to identify the digital code that causes the first input to approximately equal the second input; and
storing, in a memory, the identified digital code corresponding to the digital compensation that causes the first input to cross the second input.

15. The apparatus of claim 13 , wherein the digital compensation block is configured to apply digital compensation by performing steps comprising:
retrieving a digital code for compensation;
adjusting the digital code based on the supply voltage; and
applying the adjusted digital code to the digital input signal to compensate for resistor mismatch before conversion of the digital input signal in the DAC.

16. A method for measuring resistor mismatch in an amplifier, the method comprising:
powering down a power stage of the amplifier, wherein the power stage is coupled to an analog output node;
driving a load attached to the analog output node from a non-power stage of the amplifier coupled to the analog output node through the power stage, wherein the load is driven to a voltage different from a common mode voltage of a digital-to-analog converter (DAC) of the amplifier;
monitoring a differential input to the non-power stage; and
adjusting a digital compensation applied to a digital input node based, at least in part, on the differential input.

17. The method of claim 16 , wherein the step of monitoring the differential input comprises comparing a first input of the differential input with a second input of the differential input, and the step of adjusting the digital compensation comprises adjusting the digital compensation to cause the first input to approximately equal the second input.

18. The method of claim 17 , wherein the step of adjusting the digital compensation comprises adjusting the digital compensation until the first input crosses the second input.

19. The method of claim 17 , further comprising storing, in a memory, a digital code corresponding to the digital compensation that causes the first input to approximately equal the second input.

20. The method of claim 16 , further comprising repeating the steps of monitoring the differential input and adjusting the digital compensation for a plurality of gain values for the amplifier.

21. An apparatus, comprising:
a digital-to-analog converter (DAC) coupled to a digital input node and to an analog input node and configured to convert a digital input signal received at the digital input node to an input analog signal at the analog input node;
an amplifier comprising an analog output node, wherein the amplifier is configured to output to the analog output node an amplified version of an input analog signal received from the analog input node;
a digital compensation block cou

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Zhu Lei
• Zhao Xin
• Melanson John L

Classifications

• H03F1/3264

  in audio amplifiers · CPC title

• H03F3/2175

  using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title

• H03F3/187

  in integrated circuits · CPC title

• H03F2201/3233

  Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion · CPC title

• H03F1/30 Primary

  Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} · CPC title