Internal plasma grid for semiconductor fabrication

US10224221B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10224221-B2
Application numberUS-201615055439-A
CountryUS
Kind codeB2
Filing dateFeb 26, 2016
Priority dateApr 5, 2013
Publication dateMar 5, 2019
Grant dateMar 5, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

First claim

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What is claimed is: 1. A method of etching a feature on a substrate, the method comprising: providing the substrate to a substrate holder in a chamber comprising a plasma generator and a grid assembly dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, wherein the grid assembly comprises at least two grids; generating a plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber; and etching the feature in the substrate by interaction of the lower zone plasma with the substrate, wherein the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and wherein the electron density in the lower zone plasma is about 5×10 9 cm −3 or less, and is less than the electron density in the upper zone plasma. 2. The method of claim 1 , further comprising applying a bias to the grid assembly. 3. The method of claim 1 , further comprising applying a bias to the substrate holder. 4. The method of claim 1 , wherein the lower zone plasma is an ion-ion plasma. 5. The method of claim 1 , further comprising rotating at least one grid of the grid assembly about an axis normal to an upper the surface of the substrate holder. 6. The method of claim 1 , further comprising changing a distance between the grids in the grid assembly. 7. The method of claim 6 , wherein the distance between the grids in the grid assemblies changes while the feature is being etched on the substrate. 8. The method of claim 1 , further comprising changing a distance between the grid assembly and a plasma generator used to produce the upper zone plasma. 9. The method of claim 8 , wherein the distance between the grid assembly and the plasma generator changes while the feature is being etched on the substrate. 10. The method of claim 1 , wherein different process gases are provided to the upper and lower sub-chambers. 11. The method of claim 1 , wherein substantially no current is generated in the grids of the grid assembly when the plasma is generated. 12. The method of claim 1 , wherein the grids of the grid assembly comprise a plurality of slots, and wherein at least one of the slots has a height to width aspect ratio between about 0.5-2. 13. A method of etching a feature on a substrate, the method comprising: providing the substrate to a substrate holder in a chamber comprising a plasma generator and a grid assembly dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, wherein the grid assembly comprises at least two grids, each grid comprising a plurality of slots, wherein at least one of the slots in at least one of the grids has a height to width aspect ratio between about 0.5-2; generating a plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber; and etching the feature in the substrate by interaction of the lower zone plasma with the substrate, wherein the lower zone plasma is an ion-ion plasma. 14. The method of claim 13 , further comprising applying a bias to the grid assembly. 15. The method of claim 13 , further comprising applying a bias to the substrate holder. 16. The method of claim 13 , further comprising rotating at least one grid of the grid assembly about an axis normal to an upper the surface of the substrate holder. 17. The method of claim 13 , further comprising changing a distance between the grids in the grid assembly while the feature is being etched on the substrate. 18. The method of claim 13 , further comprising changing a distance between the grid assembly and a plasma generator used to produce the upper zone plasma while the feature is being etched on the substrate. 19. The method of claim 13 , wherein different process gases are provided to the upper and lower sub-chambers. 20. The method of claim 13 , wherein substantially no current is generated in the grids of the grid assembly when the plasma is generated.

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What does patent US10224221B2 cover?
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P72/0421. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).