Method of growing nitride semiconductor layer, nitride semiconductor device, and method of fabricating the same
US-2015380237-A1 · Dec 31, 2015 · US
US10224201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10224201-B2 |
| Application number | US-201715675230-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 11, 2017 |
| Priority date | Feb 23, 2015 |
| Publication date | Mar 5, 2019 |
| Grant date | Mar 5, 2019 |
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Provides is a C-plane GaN substrate which, although formed from a GaN crystal grown so that surface pits are generated, is free from any inversion domain, and moreover, has a low spiral dislocation density in a gallium polar surface. Provides is a C-plane GaN substrate wherein: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on a gallium polar surface; the spiral dislocation density is less than 1×106 cm−2 anywhere on the gallium polar surface; and the substrate is free from any inversion domain. The C-plane GaN substrate may comprise a high dislocation density part having a dislocation density of more than 1×107 cm−2 and a low dislocation density part having a dislocation density of less than 1×106 cm−2 on the gallium polar surface.
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The invention claimed is: 1. A C-plane GaN substrate comprising: a plurality of facet growth areas each having a closed ring outline-shape on a gallium polar surface, wherein a spiral dislocation density is less than 1×10 6 cm −2 anywhere on the gallium polar surface, and the gallium polar surface is free from any inversion domain. 2. The C-plane GaN substrate according to claim 1 , wherein the spiral dislocation density is less than 8×10 5 cm −2 anywhere on the gallium polar surface. 3. The C-plane GaN substrate according to claim 1 , wherein the substrate comprises a high dislocation density part having a dislocation density of more than 1×10 7 cm −2 and a low dislocation density part having a dislocation density of less than 1×10 6 cm −2 on the gallium polar surface. 4. The C-plane GaN substrate according to claim 3 , wherein, when the entire gallium polar surface is comparted into 100-μm square compartments, 1% or more of all the compartments each have a dislocation density of less than 1×10 5 cm −2 . 5. The C-plane GaN substrate according to claim 1 , wherein the substrate is doped with oxygen. 6. The C-plane GaN substrate according to claim 1 , wherein the substrate is doped with either or both of silicon and germanium. 7. The C-plane GaN substrate according to claim 1 , wherein the substrate has an electrical resistivity of 0.1 Ω·cm or less. 8. The C-plane GaN substrate according to claim 1 , wherein the plurality of facet growth areas are at least partially regularly arranged on the main surface. 9. A method for producing a nitride semiconductor device, comprising a step of preparing the C-plane GaN substrate according to claim 1 , and a step of epitaxially growing at least one nitride semiconductor layer on the prepared C-plane GaN substrate. 10. A method for producing an epitaxial wafer, comprising a step of preparing the C-plane GaN substrate according to claim 1 , and a step of epitaxially growing at least one nitride semiconductor layer on the prepared C-plane GaN substrate. 11. A C-plane GaN substrate having a gallium polar surface, the substrate comprising: a plurality of facet growth areas each having a closed ring outline-shape on the gallium polar surface, wherein when a virtual square grid of 2 cm×2 cm is drawn on the gallium polar surface, each cell of the grid comprises at least one 1 cm×1 cm square area in which a spiral dislocation density is anywhere less than 1×10 6 cm −2 , and the gallium polar surface is free from any inversion domain. 12. The C-plane GaN substrate according to claim 11 , wherein each cell of the grid comprises at least one 1 cm×1 cm square area in which a spiral dislocation density is anywhere less than 8×10 5 cm −2 . 13. The C-plane GaN substrate according to claim 11 , wherein the substrate comprises a high dislocation density part having a dislocation density of more than 1×10 7 cm −2 and a low dislocation density area having a dislocation density of less than 1×10 6 cm −2 on the gallium polar surface. 14. The C-plane GaN substrate according to claim 13 , wherein, when the entire gallium polar surface is comparted into compartments of 100 μm-square, 1% or more of all the compartments each have a dislocation density of less than 1×10 5 cm −2 . 15. The C-plane GaN substrate according to claim 11 , wherein the substrate is doped with oxygen. 16. The C-plane GaN substrate according to claim 11 , wherein the substrate is doped with either or both of silicon and germanium. 17. The C-plane GaN substrate according to claim 11 , wherein the substrate has an electrical resistivity of 0.1 Ω·cm or less. 18. The C-plane GaN substrate according to claim 11 , wherein the plurality of facet growth areas are at least partially regularly arranged on the main surface. 19. A method for producing a nitride semiconductor device, comprising a step of preparing the C-plane GaN substrate according to claim 11 , and a step of epitaxially growing at least one nitride semiconductor layer on the prepared C-plane GaN substrate. 20. A method for producing an epitaxial wafer, comprising a step of preparing the C-plane GaN substrate according to claim 11 , and a step of epitaxially growing at least one nitride semiconductor layer on the prepared C-plane GaN substrate.
Crystal orientation · CPC title
N-type · CPC title
Doping during depositing · CPC title
Nitrides · CPC title
Lateral overgrowth · CPC title
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