Automated attribute propagation and hierarchical consistency checking for non-standard extensions

Patent metadata

Field	Value
Publication number	US-10223487-B2
Application number	US-201715430864-A
Country	US
Kind code	B2
Filing date	Feb 13, 2017
Priority date	Aug 11, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

First claim

What is claimed is:

1. A computer-implemented method for automated attribute propagation and hierarchical consistency checking, the method comprising:
detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design, wherein detecting a non-standard extension comprises a NOBUFFER attribute being added to a voltage sense line in the integrated circuit design;
propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and
verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies,
wherein the NOBUFFER attribute is stored into a non-standard extensions file for each level of the plurality of hierarchies that the voltage sense line traverses, and wherein the non-standard extensions file indicates which of a plurality of pins should receive the NOBUFFER attribute for each level of the plurality of hierarchies, and
wherein an integrated circuit is manufactured using the integrated circuit design.

2. The computer-implemented method of claim 1 , wherein detecting a non-standard extension comprises a logic designer adding the NOBUFFER attribute to the voltage sense line in the integrated circuit design.

3. The computer-implemented method of claim 1 , wherein verifying the hierarchy consistency further comprises checking to ensure that the non-standard extension is correctly propagated through each of the plurality of hierarchies.

4. The computer-implemented method of claim 3 , wherein verifying the hierarchy consistency further comprises checking to ensure that the non-standard extension transfers from the integrated circuit logic design to a physical design for the integrated circuit.

5. The computer-implemented method of claim 4 , wherein verifying the hierarchy consistency further comprises performing a post-layout checking to ensure that a buffering tool did not add any additional buffers to the physical design for the integrated circuit.

6. The computer-implemented method of claim 5 , wherein the buffering tool comprises at least one of a buffering tool, a timing tool, and a delay tool.

7. The computer-implemented method of claim 1 , wherein the special constraint comprises at least one of a noise requirement, a timing requirement, a static voltage requirement, and a transient voltage requirement.

Assignees

• IBM

Inventors

• Averill Iii Robert M
• Behnen Erwin
• Wolpert David S

Classifications

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F17/5045

  Physics · mapped topic

• G06F17/504 Primary

  Physics · mapped topic