Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset

Patent metadata

Field	Value
Publication number	US-10223112-B2
Application number	US-201715721799-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Dec 22, 2011
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A system comprising:
an integrated memory controller unit; and
a processor core coupled to the integrated memory controller unit, the processor core comprising:
a plurality of vector registers, including a destination vector register;
a plurality of general-purpose registers;
a plurality of mask registers;
a decoder to decode an instruction specifying an integer offset, specifying an integer stride, and having a field specifying the destination vector register, wherein the instruction has one of an immediate specifying the integer offset and a field specifying a source register specifying the integer offset, wherein the instruction has one of an immediate specifying the integer stride and a field specifying a source register specifying the integer stride; and
an execution unit coupled to the decoder and coupled to the plurality of vector registers, the execution unit to execute the instruction to generate and store a result in the destination vector register, the result including a sequence of at least eight integer indexes in numerical order, in which a least significant integer index of the sequence is equal to the integer offset, and in which all integer indexes of the sequence in consecutive positions differ by the integer stride.

2. The system of claim 1 , wherein the instruction has the immediate specifying the integer offset, and the instruction has the field specifying source the register specifying the integer stride.

3. The system of claim 1 , wherein the instruction has the immediate specifying the integer stride, and the instruction has the field specifying the source register specifying the integer offset.

4. The system of claim 1 , wherein the instruction has one or more immediates specifying the integer offset and the integer stride.

5. The system of claim 1 , wherein the instruction has one or more fields specifying one or more source registers specifying the integer offset and the integer stride.

6. The system of claim 1 , wherein the result is to include the sequence of at least thirty-two integer indexes in the numerical order.

7. The system of claim 1 , wherein the destination vector register comprises 512-bits.

8. The system of claim 1 , wherein the processor core further comprises:
a level 1 cache; and
a level 2 cache.

9. The system of claim 8 , further comprising a level 3 cache.

10. The system of claim 1 , wherein the decoder and the execution unit are included in an out-of-order core, and wherein the out-of-order core comprises a reorder buffer (ROB).

11. The system of claim 1 , wherein the processor core is a reduced instruction set computing (RISC) processor core.

12. The system of claim 1 , further comprising a ring interconnect unit coupling the processor core to the integrated memory controller unit.

13. The system of claim 1 , further comprising a plurality of coprocessors coupled with the processor core.

14. The system of claim 1 , further comprising a general purpose graphics processing unit (GPGPU) coupled with the processor core.

15. The system of claim 1 , further comprising a network processor coupled with the processor core.

16. The system of claim 1 , further comprising a communication processor coupled with the processor core.

17. The system of claim 1 , further comprising a direct memory access (DMA) unit coupled with the processor core by at least an interconnect.

18. The system of claim 1 , further comprising an audio processor coupled with the processor core by at least an interconnect.

19. The system of claim 1 , further comprising an image processor coupled with the processor core by at least an interconnect.

20. The system of claim 1 , further comprising a display unit coupled with the processor core, the display unit to couple to one or more displays.

21. The system of claim 1 , further comprising a compression engine coupled with the processor core.

22. The system of claim 1 , further comprising a high-throughput processor coupled with the processor core.

23. A system comprising:
an integrated memory controller unit; and
a processor core coupled to the integrated memory controller unit, wherein the processor core is a reduced instruction set computing (RISC) processor core, the processor core comprising:
a plurality of vector registers, including a destination vector register that has 512-bits;
a plurality of general-purpose registers;
a plurality of mask registers;
a reorder buffer (ROB);
a decoder to decode an instruction having an immediate to specify an integer offset, having a field to specify a source register that is to specify an integer stride, and having a field to specify the destination vector register; and
an execution unit coupled to the decoder and coupled to the plurality of vector registers, the execution unit to execute the instruction to generate and store a result in the destination vector register, the result including a sequence of at least thirty-two integer indexes in numerical order, in which a least significant integer index of the sequence is equal to the integer offset, and in which all integer indexes of the sequence in consecutive positions differ by the integer stride; and
a network processor coupled with the processor core.

Assignees

• Intel Corp

Inventors

• Abraham Seth
• Ould-Ahmed-Vall Elmoustapha
• Valentine Robert
• Sperber Zeev
• Gradstein Amit

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3455

  using stride · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title