Network controller-sideband interface port controller

Patent metadata

Field	Value
Publication number	US-10218635-B2
Application number	US-201514857952-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Nov 7, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A network interface controller (NC) that can provide a connection for a device to a network. The NC can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can communicate information with the network via the sideband. The sideband port controller can include a receive data route that has an input for receiving packets of data from the network and an output for passing the packets of data received from the network to the sideband endpoint circuit. The receive data route may include a buffer to receive the packets of data from the network and to pass the packets of data received from the network to the sideband endpoint.

First claim

What is claimed is:

1. A network interface controller for providing a connection for a device to a network, the network interface controller comprising a sideband port controller, the sideband port controller for providing a sideband connection between the network and a sideband endpoint circuit that is operative to communicate information with the network via a sideband, the sideband port controller comprising:
a receive data route having an input for receiving packets from the network via a receive backbone unit and an output for passing the packets received from the network to the sideband endpoint circuit, the receive data route comprising a receive buffer to receive the packets from the network and to pass the packets received from the network to the sideband endpoint circuit, wherein the receive buffer includes an overrun mechanism configured to drop received packets when the receive buffer has no available bandwidth;
a receive arbiter and one or more other data sources of the sideband port controller, the receive arbiter configured to determine whether the received packets from the receive buffer or data from a data source of the one or more other data sources of the sideband port controller is to be forwarded via the output of the sideband port controller to the sideband endpoint circuit;
a packet injection register (PIR) that is configured to accept sideband packets when the PIR has available bandwidth to store the sideband packets, wherein the sideband packets are packets received from the sideband endpoint circuit;
a latch configured to be set when an end-of-packet (EOP) marker signals that the PIR has no available bandwidth;
a packet injection arbiter (PIA) configured to select the sideband packets to be forwarded to an output XS 1 buffer, and to prioritize forwarding the sideband packets to an XS 2 buffer over forwarding the sideband packets to the output XS 1 buffer, wherein both the output XS 1 buffer and the XS 2 buffer are connected to the receive data route, wherein the PIA is connected to a leak mechanism that forwards the sideband packets to the network, wherein the output XS 1 buffer transmits received sideband packets to a main media access controller (MAC);
a counter configured to increment when an in-band packet is advanced, along the receive data route, from the output XS 1 buffer to the XS 2 buffer and to reset when any sideband packet is advanced from the network interface controller, wherein the PIA is arranged to allow the sideband packet to advance when the counter has reached a certain value;
a packet engage latch that is set when either the output XS 1 buffer or the XS 2 buffer is selected to receive either the in-band packet or the sideband packet, wherein the packet engage latch is in the PIA; and
a transfer logic block configured to stop data packets from being transferred by the XS 2 buffer and the PIR in response to receiving a signal indicating that the XS 1 buffer is full.

2. The network interface controller as claimed in claim 1 , wherein the sideband port controller further comprises the main MAC for communicating with the sideband endpoint circuit, wherein the output XS 1 buffer is configured to receive any forwarded packets, wherein the XS 2 buffer is configured to receive data packets that are not in-band data packets or sideband packets from a host into the receive backbone unit, the receive backbone unit being configured to manage movement of data from the main MAC by converting, aligning, and storing data into a line buffer, the network interface controller further comprising:
the PIA, wherein the PIA is configured to allow, at a time, the in-band packet to advance along the receive data route from a host buffer to the main MAC and further connected to allow, at a different time, the sideband packet to advance along the receive data route from a sideband buffer to the main MAC.

3. The network interface controller as claimed in claim 2 , wherein the one or more other data sources further comprises a packet parser of the sideband port controller.

4. The network interface controller as claimed in claim 3 , wherein the packet parser is operative to identify sideband packets of data from the sideband endpoint circuit that contain a command from the sideband port controller, the sideband port controller is operative to compile a response packet in response to the command, and the sideband port controller is operative to insert the response packet into the receive data route.

5. The network interface controller as claimed in claim 3 , wherein the sideband port controller further comprises an event notification unit that is operative to compile indications into an event notification packet and further operative to pass the event notification packet to the packet parser, and the sideband port controller is operative to insert the event notification packet into the receive data route.

6. The network interface controller as claimed in claim 5 , wherein the receive data route is operative to give priority to the event notification packet over the packets from the network.

7. The network interface controller as claimed in claim 1 , wherein the receive data route is further operative to drop the packets that are received from the network in a case of overflow.

8. The network interface controller as claimed in claim 1 , the network interface controller further comprising:
an extractor operative to extract packets from a stream of packets from the network received by the main MAC; and
wherein the main MAC is operative to forward packets that are recognized as sideband traffic to the receive data route of the sideband port controller.

9. The network interface controller of claim 1 , wherein the output XS 1 buffer is configured to receive any forwarded packets, wherein the XS 2 buffer is configured to receive priority over the output XS 1 buffer and receive data packets that are not in-band data packets or sideband packets from a host into the receive backbone unit, the receive backbone unit being configured to manage movement of data from a media access controller (MAC) by converting, aligning, and storing the data into a line buffer, the network interface controller further comprising:
the PIA, wherein the PIA is configured to allow, at a time, the in-band packet to advance along the receive data route from a host buffer to the MAC and further connected to allow, at a different time, the sideband packet to advance along the receive data route from a sideband buffer to the MAC.

10. The network interface controller of claim 9 , further comprising:
an RS 1 X buffer and an RS 2 X buffer configured to receive data packets that are not in-band packets or sideband packets from the main MAC and to transmit the received data packets to a multiplexor, wherein the RS 1 X buffer and the RS 2 X buffer are within the receive backbone unit;
a scheduler configured to determine which of the RS 1 X buffer and the RS 2 X buffer is selected to transmit a next data packet to a decoder, wherein the decoder is configured to read a header of the data packets and is further configured to set a second latch in response to the header indicating that the data packets are destined for a baseboard management controller, wherein the second latch is configured to be reset when a second EOP marker is identified; and
a write scheduler for transmitting a write pulse to an action machine in response to the setting of the second latch.

11. A method of receiving data in a network interface controller providing a connection for a device to a network, the network interface controller comprising a sideband port controller, the sideband port controller providing a sideband connection betwe

Assignees

• IBM

Inventors

• Aldebert Jean-Paul
• Basso Claude
• Frenoy Jean-Luc
• Verplanken Fabrice J

Classifications

• H04L47/801 Primary

  Real time traffic · CPC title

• H04L47/2466

  using signalling traffic · CPC title

• H04L69/22 Primary

  Parsing or analysis of headers · CPC title

• H04L69/26

  Special purpose or proprietary protocols or architectures (network applications for proprietary or special purpose networking environments H04L67/12) · CPC title

• H04L67/125

  involving control of end-device applications over a network · CPC title