Network controller-sideband interface port controller

Patent metadata

Field	Value
Publication number	US-10218634-B2
Application number	US-201514857930-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Nov 7, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A network interface controller for providing a connection for a device to a network. The network interface controller may include a sideband port controller. The sideband port controller may provide a sideband connection between the network and a sideband endpoint circuit that is operative to communicate information with the network via the sideband. The sideband port controller may include a transmit data route having an input for receiving packets from the sideband endpoint circuit and an output for passing packets received from the sideband endpoint to the network. A packet parser is connected to the transmit data route. The packet parser is operative to read data from packets received from the sideband endpoint and is further operative to analyze the data.

First claim

What is claimed is:

1. A network interface controller for providing a connection for a device to a network, the network interface controller comprising a sideband port controller, the sideband port controller for providing a sideband connection between the network and a sideband endpoint circuit that is operative to communicate information with the network via a sideband, the sideband port controller comprising:
a transmit data route having an input for receiving sideband packets from the sideband endpoint circuit and an output for passing the sideband packets received from the sideband endpoint circuit to the network;
a packet parser connected to the transmit data route, the packet parser operative to read data from the sideband packets received from the sideband endpoint circuit and further operative to analyze the read data;
a packet injection register (PIR) that is configured to accept the sideband packets when the PIR has available bandwidth to store the sideband packets;
a latch configured to be set when an end-of-packet (EOP) marker signals that the PIR has no available bandwidth;
a packet injection arbiter (PIA) configured to select the sideband packets to be forwarded to an output XS 1 buffer, and to prioritize forwarding the sideband packets to an XS 2 buffer over forwarding the sideband packets to the output XS 1 buffer, wherein both the output XS 1 buffer and the XS 2 buffer are connected to the transmit data route, wherein the PIA is connected to a leak mechanism that forwards the sideband packets to the network, wherein the output XS 1 buffer transmits received sideband packets to a main media access controller (MAC);
a counter configured to increment when an in-band packet is advanced, along the transmit data route, from the output XS 1 buffer to the XS 2 buffer and to reset when any sideband packet is advanced from the network interface controller, wherein the PIA is arranged to allow the sideband packet to advance when the counter has reached a certain value;
a packet engage latch that is set when either the output XS 1 buffer or the XS 2 buffer is selected to receive either the in-band packet or the sideband packet, wherein the packet engage latch is in the PIA; and
a transfer logic block configured to stop data packets from being transferred by the XS 2 buffer and the PIR in response to receiving a signal indicating that the XS 1 buffer is full.

2. The network interface controller as claimed in claim 1 , wherein the transmit data route further comprises a buffer to receive the sideband packets from the sideband endpoint circuit and to forward the sideband packets received from the sideband endpoint circuit to the network.

3. The network interface controller as claimed in claim 1 , wherein the packet parser is further operative to indicate that a sideband packet of the received sideband packets is to be passed to the network, and the transmit data route is operative to, responsive to an indication to pass the packet, output the sideband packet.

4. The network interface controller as claimed in claim 1 , wherein the packet parser is further operative to indicate that a sideband packet contains a command for the sideband port controller, the sideband port controller is further operative to respond to the command by compiling a response to the command, and the sideband port controller is further operative to forward the compiled response to the sideband endpoint circuit.

5. The network interface controller as claimed in claim 1 , wherein the sideband port controller further comprises a receive data route having an input for receiving the sideband packets from the network and an output for passing the sideband packets received from the network to the sideband endpoint circuit, and the sideband port controller further comprises a receive arbiter operative to, responsive to a command, forward the packets received by the sideband port controller from the network to the sideband endpoint circuit.

6. The network interface controller as claimed in claim 5 , wherein the packet parser is arranged to scan through the sideband packets that are received from the network for the EOP marker.

7. The network interface controller as claimed in claim 1 , wherein the sideband port controller further comprises an event notification unit for compiling indications into an event notification packet, the sideband port controller further operative to pass the event notification packet to the transmit data route, the packet parser further operative to indicate that a sideband packet contains the event notification packet, the sideband port controller further operative to respond to the indication by forwarding information in the event notification packet to the sideband endpoint circuit.

8. The network interface controller as claimed in claim 1 , wherein the transmit data route has a pause mechanism, the pause mechanism operative to prevent the sideband packets received from the sideband endpoint circuit from advancing along the transmit data route if blocked by a condition ahead of them.

9. The network interface controller as claimed in claim 1 , wherein the sideband port controller further comprises a MAC, the MAC operative to communicate with the sideband endpoint circuit.

10. The network interface controller as claimed in claim 1 ,
wherein the main MAC is operative to connect to the network, and wherein the network interface controller further comprises an injector unit operative to insert the sideband packets from the output of the transmit data route into a stream of packets being transmitted to the network by the main MAC.

11. The network interface controller of claim 1 , wherein the output XS 1 buffer is configured to receive any forwarded packets, wherein the XS 2 buffer is configured to receive priority over the output XS 1 buffer and receive data packets that are not in-band data packets or sideband packets from a host into a receive backbone unit, the receive backbone unit being configured to manage movement of data from a media access controller (MAC) by converting, aligning, and storing data into a line buffer, the network interface controller further comprising:
the PIA, wherein the PIA is configured to allow, at a time, the in-band packet to advance along the transmit data route from a host buffer to the MAC and further connected to allow, at a different time, the sideband packet to advance along the transmit data route from a sideband buffer to the MAC.

12. The network interface controller of claim 11 , further comprising:
a RS 1 X buffer and a RS 2 X buffer configured to receive data packets that are not in-band packets or sideband packets from the main MAC and to transmit the received data packets to a multiplexor, wherein the RS 1 X buffer and the RS 2 X buffer are within the receive backbone unit;
a scheduler configured to determine which of the RS 1 X buffer and the RS 2 X buffer is selected to transmit a next data packet to a decoder, wherein the decoder is configured to read a header of the data packets and is further configured to set a second latch in response to the header indicating that the data packets are destined for a baseboard management controller, wherein the second latch is configured to be reset when a second EOP marker is identified; and a write scheduler for transmitting a write pulse to an action machine in response to the setting of the second latch.

13. A method of transmitting data in a network interface controller for providing a connection for a device to a network, the network interface controller comprising a sideband port controller, the sideband port controller operative to provide a sideband connection betw

Assignees

• IBM

Inventors

• Aldebert Jean-Paul
• Basso Claude
• Frenoy Jean-Luc
• Verplanken Fabrice J

Classifications

• H04L47/2466

  using signalling traffic · CPC title

• H04L69/22 Primary

  Parsing or analysis of headers · CPC title

• H04L47/801 Primary

  Real time traffic · CPC title

• G06F2213/3808

  Network interface controller · CPC title

• H04L67/125

  involving control of end-device applications over a network · CPC title