Low power bidirectional bus

Patent metadata

Field	Value
Publication number	US-10218535-B2
Application number	US-201815898839-A
Country	US
Kind code	B2
Filing date	Feb 19, 2018
Priority date	Mar 9, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

First claim

The invention claimed is:

1. An audio system, comprising:
a host device;
an accessory product, wherein the accessory product comprises two components, wherein each component is configured for bidirectional data transfer between the component and the host device; and
a signal bus, comprising first and second signal lines, wherein the signal bus connects the host device and the accessory product;
wherein the host device is configured to generate a clock signal, and impose the clock signal on the first line of the signal bus;
wherein each component of the accessory product is configured to transmit a first pattern of bit values to the host device on the second line of the signal bus, during a respective subset of first half-periods of each period of said clock signal;
wherein the host device is configured to transmit a second pattern of bit values to the accessory product on the second line of the signal bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal;
wherein, in order to transmit information from the host device to the accessory product, the host device is configured to transmit an altered second pattern of bit values; and
wherein, in order to transmit information to the host device, each component of the accessory product is configured to transmit an altered first pattern of bit values.

2. An audio system as claimed in claim 1 , wherein the host device and the accessory product are further configured such that, in an alternative mode of operation, the signal bus is operated as a differential signal bus, wherein the first and second lines of the signal bus operate as a positive signal line and a negative signal line of the differential signal bus.

3. An audio system as claimed in claim 1 , wherein the second pattern of bit values is the same as the first pattern of bit values, such that transmitting the second pattern of bit values from the host device to the accessory product requires maintaining a signal level on the second line of the signal bus.

4. An audio system as claimed in claim 1 , wherein the first pattern of bit values is a Barker code sequence.

5. An audio system as claimed in claim 1 , wherein the second pattern of bit values is a Barker code sequence.

6. An audio system as claimed in claim 1 , wherein the altered second pattern of bit values is the second pattern of bit values inverted.

7. An audio system as claimed in claim 1 , wherein the altered first pattern of bit values is the first pattern of bit values inverted.

8. An audio system as claimed in claim 1 , wherein the accessory product is configured to switch to a low power mode of operation in response to the host device transmitting information to the accessory product by transmitting the altered second pattern of bit values.

9. An audio system as claimed in claim 1 , wherein the host device and the accessory product are provided in a single product.

10. An audio system as claimed in claim 1 , wherein the host device and the accessory product are provided in first and second devices, respectively, the first and second devices being connected by a wired connection.

11. An audio system as claimed in claim 10 , wherein the second device is detachably connected to the first device.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Zwart Willem
• Bowlerwell John Bruce
• Page Michael
• Boomer Alastair

Classifications

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L12/40013 Primary

  Details regarding a bus controller · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• H04L5/1476

  operating bitwise · CPC title