Techniques for low complexity soft decoder for turbo product codes

Patent metadata

Field	Value
Publication number	US-10218388-B2
Application number	US-201615173446-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Dec 18, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

First claim

What is claimed is:

1. A method for decoding, comprising:
obtaining a first message comprising a plurality of information bits and a plurality of parity bits from a memory via a channel;
decoding, using a Chase decoder the first message using an iterative decoding algorithm to generate a first bit sequence;
identifying locations of bits flipped by the Chase decoder based on the first bit sequence and the first message, the locations of the bits flipped corresponding to a first bit flip pattern;
generating a miscorrection metric based on reliability values corresponding to bits in the first message at the locations of the bits flipped; and
performing a miscorrection avoidance thresholding (MAT) decoding procedure by:
determining whether a miscorrection happened in an iteration of the iterative decoding algorithm by comparing the miscorrection metric with an adaptive threshold, wherein the adaptive threshold has a value that changes and is defined based on a counter of the iteration, and wherein the value increases with an increase to the counter;
upon determining that the miscorrection did happen based at least in part on the comparing of the miscorrection metric with the adaptive threshold:
declaring a decoded pattern to constitute an error
performing an additional decoding iteration by the Chase decoder of the first message based on a second bit flip pattern; and
increasing the value of the adaptive threshold; and

upon determining that the miscorrection did not happen, outputting the first bit sequence as a decoded message without repeating the decoding of the first message based on the second bit flip pattern.

2. The method of claim 1 , wherein the decoding the first message comprises:
selecting a first set of least reliable bits from the first message by comparing one or more reliability values corresponding to one or more bits in the first message with a first reliability threshold;
generating one or more bit flipping patterns based on the first set of least reliable bits; and
generating the first bit sequence using the first message and the one or more bit flipping patterns.

3. The method of claim 2 , wherein if a number of bits in the first set of least reliable bits is smaller than a predefined value, selecting a second set of least reliable bits by comparing the one or more reliability values with a second reliability threshold, wherein the second threshold is greater than the first threshold.

4. The method of claim 2 , wherein each bit flipping pattern comprises a maximum number of flipped bits which is smaller than a number of least reliable bits in the first message.

5. The method of claim 1 , wherein the first message corresponds to a turbo product code (TPC) codeword comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes.

6. An apparatus for decoding, comprising:
a memory;
at least one processor coupled to the memory, the at least one processor configured to:
obtain a first message comprising a plurality of information bits and a plurality of parity bits from a memory via a channel;
decode the first message using an iterative decoding algorithm to generate a first bit sequence;
identify locations of bits flipped by the decoding based on the first bit sequence and the first message, the locations of the bits flipped corresponding to a first bit flip pattern;
generate a miscorrection metric based on reliability values corresponding to bits in the first message at the locations of the bits flipped;
determine whether a miscorrection happened in an iteration of the iterative decoding algorithm by comparing the miscorrection metric with an adaptive threshold, wherein the adaptive threshold has a value that changes and is defined based on a counter of the iteration, and wherein the value increases with an increase to the counter;
upon determining that the miscorrection did happen based at least in part on the comparing of the miscorrection metric with the adaptive threshold:
declaring a decoded pattern to constitute an error, and
performing, by using the iterative decoding algorithm, an additional decoding iteration of the first message based on a second bit flip pattern and on an increase to the value of the adaptive threshold; and

upon determining that the miscorrection did not happen, output the first bit sequence as a decoded message without repeating the decoding of the first message based on the second bit flip pattern.

7. The apparatus of claim 6 , wherein the processor is further configured to:
select a first set of least reliable bits from the first message by comparing one or more reliability values corresponding to one or more bits in the first message with a first reliability threshold;
generate one or more bit flipping patterns based on the first set of least reliable bits; and
generate the first bit sequence using the first message and the one or more bit flipping patterns.

8. The apparatus of claim 7 , wherein the processor is further configured to select a second set of least reliable bits by comparing the one or more reliability values with a second reliability threshold if a number of bits in the first set of least reliable bits is smaller than a predefined value, wherein the second threshold is greater than the first threshold.

9. The apparatus of claim 7 , wherein each bit flipping pattern comprises a maximum number of flipped bits which is smaller than a number of least reliable bits in the first message.

10. The apparatus of claim 6 , wherein the first message corresponds to a turbo product code (TPC) codeword comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes.

11. A non-transitory processor-readable medium for decoding, comprising processor-readable instructions configured to cause one or more processors to:
obtain a first message comprising a plurality of information bits and a plurality of parity bits from a memory via a channel;
decode the first message using an iterative decoding algorithm to generate a first bit sequence;
identify locations of bits flipped by the decoding based on the first bit sequence and the first message, the locations of the bits flipped corresponding to a first bit flip pattern;
generate a miscorrection metric based on reliability values corresponding to bits in the first message at the locations of the bits flipped;
determine whether a miscorrection happened in an iteration of the iterative decoding algorithm by comparing the miscorrection metric with an adaptive threshold, wherein the adaptive threshold has a value that changes and is defined based on a counter of the iteration, and wherein the value increases with an increase to the counter;
upon determining that the miscorrection did happen based at least in part on the comparing of the miscorrection metric with the adaptive threshold:
declaring a decoded pattern to constitute an error, and
performing, by using the iterative decoding algorithm, an additional decoding iteration of the first message based on a second bit flip pattern and on an increase to the value of the adaptive threshold; and

upon determining that the miscorrection did not happen, output the first bit sequence as a decoded message without repeating the decoding of the first message based on the second bit flip pattern.

12. The processor-readable medium of claim 11 , wherein the processor-readable instructions are further configured to cause the one or more processors to:
select a first set of least reliable bits from the first message by comparing one or more reliability values corresponding to one or more bits in t

Assignees

• Sk Hynix Inc

Inventors

• Lin Yi-Min
• Bhatia Aman
• Kumar Naveen
• Yen Johnson

Classifications

• H03M13/6561

  Parallelized implementations · CPC title

• G11C2029/0409

  Online test · CPC title

• H03M13/2963 Primary

  Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• H03M13/2957

  Turbo codes and decoding · CPC title