Transformer phase permutation causing more uniform transformer phase aging and general switching network suitable for same

Patent metadata

Field	Value
Publication number	US-10218300-B2
Application number	US-201715823912-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Feb 28, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method includes determining whether transformer phases should be permuted. The method includes, responsive to a determination that the transformer phases should be permuted, permuting the transformer phases, based on historical aging information of transformer input phases, to cause transformer input phases with higher ages to be connected to transformer output phases with lower output loads and transformer input phases with lower ages to be connected to transformer output phases with higher output loads. Multiple apparatus and program products are also disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a first sorting network comprising a first logic circuit configured to sort input signals A, B, C, wherein the sorting is performed so the signals A, B, C are always in a first particular order based on values of the signals A, B, C, and wherein the first logic circuit is further configured to connect the input signals A, B, C to first outputs based on the first particular order;
a second sorting network comprising a second logic circuit configured to sort output signals A 0 , B 0 , C 0 to second outputs based on values of the output signals A 0 , B 0 , C 0 , wherein the sorting is performed so the second outputs are always in a second particular order based on the values of the output signals A 0 , B 0 , C 0 , and wherein the second logic circuit is further configured to connect the second outputs to the output signals A 0 , B 0 , C 0 , based on the second particular order; and
connection circuitry configured so that first outputs and the second outputs are connected so the first outputs with lower input-signal values in the first particular order are connected to second outputs with higher output-signal values in the second particular order and the first outputs with higher input-signal values in the first particular order are connected to second outputs with lower output-signal values in the second particular order, wherein:
the first logic circuit is configured to sort input transformer phases to age-sorted phases based on historical aging information for the input transformer phases, wherein the sorting is performed so the age-sorted phases are always in a first particular order based on corresponding ages of the input transformer phases, the first logic circuit further configured to connect the transformer input phases to outputs for the age-sorted phases based on the first particular order;
the second logic circuit is configured to sort transformer output phases to load-sorted phases based on output load for each of the transformer output phases, wherein the sorting is performed so the load-sorted phases are always in a second particular order based on the output loads, wherein the second logic circuit is further configured to connect the inputs for the load-sorted phases to the output transformer phases based on the second particular order; and
the connection circuitry is configured so that load-sorted phases and the age-sorted phases are connected so the outputs for the age-sorted phases with lower age are connected to inputs for load-sorted phases with higher output loads and the outputs for the age-sorted phases with higher age are connected to inputs for load-sorted phases with lower output loads.

2. The apparatus of claim 1 , wherein there are three input transformer phases, and there are three output transformer phases.

3. The apparatus of claim 2 , wherein the first logic circuit outputs three signals s 0 , s 1 , s 2 , the second logic circuit outputs three signals t 0 , t 1 , t 2 , and the apparatus further comprises three multiplexors, where each multiplexor selects a corresponding one of three resultant loads based on the signals s 0 , s 1 , s 2 , the signals t 0 , t 1 , t 2 , and the output loads, wherein each of the three resultant loads is a load on a corresponding one of the three transformer phases.

4. The apparatus of claim 3 , wherein each multiplexor performs a 36-way selection based on permutations of combinations of possible output loads and possible resultant loads.

5. The apparatus of claim 3 , further comprising:
three adders, each adder adding a corresponding one of the resultant loads, after conversion to an age, with a previous value of historical aging information for a corresponding one of the input phases; and
three latches, each latch latching an output of a corresponding one of the three adders.

6. The apparatus of claim 2 , wherein the first logic circuit outputs three signals s 0 , s 1 , s 2 , the second logic circuit outputs three signals t 0 , t 1 , t 2 , and the permutation circuit further comprises at least one processor, which in response to executing computer-readable code selects a corresponding one of three resultant loads based on the signals s 0 , s 1 , s 2 , the signals t 0 , t 1 , t 2 , and the output loads, wherein each of the three resultant loads is a load on a corresponding one of the three transformer phases.

Assignees

• IBM

Inventors

• Ditlow Gary S
• Phan Dung T
• Xiong Jinjun

Classifications

• G01R31/62

  Testing of transformers · CPC title

• Y02E40/50

  Arrangements for eliminating or reducing asymmetry in polyphase networks · CPC title

• H02J3/26

  Arrangements for eliminating or reducing asymmetry in polyphase networks · CPC title

• H02P13/06 Primary

  by tap-changing; by rearranging interconnections of windings · CPC title

• H01F30/14

  for changing the number of phases · CPC title