Insulated synchronous rectification DC/DC converter

US10218283B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10218283-B2
Application numberUS-201514980508-A
CountryUS
Kind codeB2
Filing dateDec 28, 2015
Priority dateDec 24, 2014
Publication dateFeb 26, 2019
Grant dateFeb 26, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

When a pulse generator detects that a switching transistor on a primary side of a DC/DC converter turns off, the pulse generator sets a pulse signal S1 to an on level configured as an instruction to turn on a synchronous rectification transistor. When the pulse generator detects that the current that flows through the secondary winding of a transformer becomes substantially zero, the pulse generator sets the pulse signal S1 to an off level configured as an instruction to turn off the synchronous rectification transistor. After a predetermined time-up period elapses after the detection of the turn-on of the switching transistor, a forced turn-off circuit forcibly turns off the synchronous rectification transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. A synchronous rectification controller to be arranged on a secondary side of an insulated synchronous rectification DC/DC converter, and structured to control a synchronous rectification transistor, and, the synchronous rectification controller comprising: a drain pin coupled to a drain of the synchronous rectification transistor; a ground pin coupled to a source of the synchronous rectification transistor; a first comparator structured to compare a drain voltage at the drain pin with a first threshold voltage, and structured to assert a set signal when the drain voltage becomes lower than the first threshold voltage; a second comparator structured to compare the drain voltage with a second threshold voltage, and structured to assert a reset signal when the drain voltage becomes higher than the second threshold voltage; a forced turn-off circuit coupled to receive the reset signal second comparator, and structured to start a time measurement operation in response to an assertion of the reset signal and to assert a forced turn-off signal so as to forcibly turn off the synchronous rectification transistor after a predetermined time-up period elapses after the assertion of the reset signal; a flip-flop structured to generate a pulse signal which is switched to an on level in response to an assertion of the set signal, and which is switched to an off level in response to an assertion of the reset signal and an assertion of the forced turn-off signal; and a third comparator structured to compare the drain voltage with a third threshold voltage configured as a predetermined positive voltage, wherein the synchronous rectification transistor turns on in response to an assertion of the set signal and turns off in response to the assertion of the reset signal, and wherein, the forced turn-off circuit is coupled to receive an output signal from the third comparator, and when the drain voltage crosses the third threshold voltage, the time measurement operation of the forced turn-off circuit is reset so as to ensure a switching operation of the synchronous rectification transistor during a discontinuous mode. 2. The synchronous rectification controller according to claim 1 , wherein, when at least one from among the reset signal and the forced turn-off signal is asserted, the flip-flop sets the pulse signal to an off level. 3. The synchronous rectification controller according to claim 1 , wherein the third threshold voltage is configured as an output voltage of the DC/DC converter. 4. The synchronous rectification controller according to claim 1 , wherein the forced turn-off circuit comprises: a capacitor having one end supplied with a fixed electric potential; a current source structured to supply a current to the capacitor; a discharge circuit structured to discharge the capacitor in response to the reset signal; a fourth comparator structured to compare a voltage across the capacitor with a fourth threshold voltage, and a one shot circuit coupled to receive an output of the fourth comparator and structured to output the forced turn-off signal which is asserted for a predetermined time period when the voltage across the capacitor exceeds the fourth threshold voltage. 5. The synchronous rectification controller according to claim 4 , wherein the current source is structured to supply a current having a current value that is adjustable according to a resistance value of an external resistor externally coupled to the current source. 6. The synchronous rectification controller according to claim 1 , monolithically integrated on a single semiconductor substrate. 7. An insulated synchronous rectification DC/DC converter comprising: a transformer comprising a primary winding and a secondary winding; the switching transistor connected to the primary winding of the transformer; the synchronous rectification transistor connected to the secondary winding of the transformer; a photocoupler; a primary-side controller that is connected to an output side of the photocoupler, and structured to switch on and off the switching transistor according to a feedback signal received from the photocoupler; the synchronous rectification controller according to claim 1 , that controls the synchronous rectification transistor; and a feedback circuit that is connected to an input side of the photocoupler, and that generates an error current that corresponds to an output voltage of the DC/DC converter. 8. A power supply apparatus comprising: a filter structured to filter a commercial AC voltage; a diode rectifier circuit structured to full-wave rectify an output voltage of the filter; a smoothing capacitor structured to smooth an output voltage of the diode rectifier circuit so as to generate a DC input voltage; and the DC/DC converter according to claim 7 , that steps down the DC input voltage, and that supplies the DC input voltage thus stepped down to a load. 9. An electronic device comprising: a load; a filter that filters a commercial AC voltage; a diode rectifier circuit that full-wave rectifies an output voltage of the filter; a smoothing capacitor that smooths an output voltage of the diode rectifier circuit so as to generate a DC input voltage; and the DC/DC converter according to claim 7 , that steps down the DC input voltage, and that supplies the DC input voltage thus stepped down to the load. 10. A power supply adapter comprising: a filter that filters a commercial AC voltage; a diode rectifier circuit that full-wave rectifies an output voltage of the filter; a smoothing capacitor that smooths an output voltage of the diode rectifier circuit so as to generate a DC input voltage; and the DC/DC converter according to claim 7 , that steps down the DC input voltage, and that supplies the DC input voltage thus stepped down to a load. 11. The synchronous rectification controller according to claim 1 , wherein the third threshold voltage is essentially equal to an output voltage of the DC/DC converter. 12. The synchronous rectification controller according to claim 1 , wherein the third threshold voltage is a voltage that is offset with respect to the output voltage. 13. The synchronous rectification controller according to claim 1 , further comprising a setting pin to be coupled to an external resistor, wherein the time-up period is determined according to a resistance value of the external resistor. 14. The synchronous rectification controller according to claim 6 , wherein the flip-flop is a D flip-flop having its D-input receiving a high level voltage, and its clock terminal receiving the set signal from the first comparator, and the synchronous rectification controller further comprises a driver having its input receiving the pulse signal output from the D flip-flop, and an output of the driver being coupled to a gate of the synchronous rectification transistor, wherein the driver is monolithically integrated on said single semiconductor substrate. 15. The synchronous rectification controller according to claim 14 , wherein the second comparator having its one input coupled to the drain pin, its another input receiving the second threshold voltage, and its output coupled to a reset terminal of the D flip-flop via an AND gate. 16. The synchronous rectification controller according to claim 15 , wherein an output of the third comparator is coupled to the forced turn-off circuit, and the output of the forced turn-off circuit is coupled to the reset terminal of the D flip-flop via the AND gate. 17. The synchronous rectification controller acc

Assignees

Inventors

Classifications

  • having at least one active switching element at the secondary side of an isolation transformer · CPC title

  • with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

  • having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer · CPC title

  • with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

  • Cross-Sectional Technologies · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10218283B2 cover?
When a pulse generator detects that a switching transistor on a primary side of a DC/DC converter turns off, the pulse generator sets a pulse signal S1 to an on level configured as an instruction to turn on a synchronous rectification transistor. When the pulse generator detects that the current that flows through the secondary winding of a transformer becomes substantially zero, the pulse gene…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/33576. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).