Asymmetric correlated electron switch operation

Patent metadata

Field	Value
Publication number	US-10217937-B2
Application number	US-201715681236-A
Country	US
Kind code	B2
Filing date	Aug 18, 2017
Priority date	Sep 10, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.

First claim

What is claimed is:

1. A correlated electron switch (CES) device comprising:
first and second terminals; and
one or more contiguous layers of a correlated electron material (CEM) formed between the first and second terminals,
wherein the one or more contiguous layers of the CEM are capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation,
wherein the one or more contiguous layers of the CEM further comprises at least one layer of intrinsic CEM and one or more doped layers of CEM, and
wherein the first write operation is asymmetric with the second write operation.

2. The CES device of claim 1 , and wherein:
the first write operation is characterized by a first write voltage condition and a first write current condition between the first and second terminals,
the second write operation is characterized by a second voltage condition and a second current condition between the first and second terminals,
a polarity of the first voltage condition is opposite a polarity of the second voltage condition, and
a magnitude of the first voltage condition is greater than a magnitude of the second voltage condition.

3. The CES device of claim 2 , wherein a polarity of the first current condition is opposite a polarity of the second current condition, and wherein a magnitude of the first current condition is greater than a magnitude of the second current condition.

4. The CES device of claim 1 , wherein the third write operation is asymmetric with the fourth write operation.

5. The CES device of claim 4 , wherein the third write operation comprises a third voltage condition and a third current condition between the first and second terminals, and the fourth write operation comprises a fourth voltage condition and a fourth current condition between the first and second terminals, and
wherein a polarity of the third voltage condition is opposite a polarity of the fourth voltage condition, and wherein a magnitude of the third voltage condition is greater than a magnitude of the fourth voltage condition.

6. The CES device of claim 5 , wherein a polarity of the third current condition is opposite a polarity of the fourth current condition, and wherein a magnitude of the third current condition is greater than a magnitude of the fourth current condition.

7. The CES device of claim 1 , wherein the one or more contiguous layers of CEM are non-uniformly doped between the first and second terminals.

8. A method comprising:
forming first and second terminals on at least a portion of one or more contiguous layers of a correlated electron material (CEM) to form a correlated electron switch (CES), wherein the CES is capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation; and
affecting a structure or composition of the one or more contiguous layers of the CEM such that the first write operation is asymmetric with the second write operation, wherein affecting the structure or composition of the one or more contiguous layers of the CEM further comprises forming the one or more contiguous layers of the CEM to comprise at least one layer of intrinsic CEM and one or more doped layers of CEM.

9. The method of 8 , wherein the CEM comprises a transition metal oxide.

10. The method of claim 8 , wherein affecting the structure or composition of the one or more contiguous layers of the CEM further affects the structure or composition of the one or more contiguous layers of the CEM such that the third write operation is asymmetric with the fourth write operation.

11. The method of claim 8 , wherein affecting the structure or composition of the one or more contiguous layers of the CEM further comprises applying a P-type doping or an N-type doping over at least a portion of the one or more contiguous layers of the CEM.

12. The method of claim 11 , and further comprising maintaining at least a portion of the one or more contiguous layers of CEM intrinsic.

13. The method of claim 11 , wherein affecting the structure or composition of the one or more contiguous layers of the CEM further comprises affecting a concentration of doping over at least a portion of the one or more contiguous layers of the CEM according to a gradient.

14. A correlated electron switch (CES) device comprising:
first and second terminals; and
one or more contiguous layers of a correlated electron material (CEM) formed between the first and second terminals,
wherein the one or more contiguous layers of the CEM are capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation,
wherein the one or more contiguous layers of CES comprise at least an intrinsic layer of CEM formed between an N-type doped layer of CEM and a P-type doped layer of CEM, and
wherein the first write operation is asymmetric with the second write operation.

15. A correlated electron switch (CES) device comprising:
first and second terminals; and
one or more contiguous layers of a correlated electron material (CEM) formed between the first and second terminals,
wherein the one or more contiguous layers of the CEM are capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation,
wherein the one or more contiguous layers of CES comprise at least an intrinsic layer of CEM formed between a first P-type doped layer of CEM and a second P-type doped layer of CEM, wherein a thickness of the first P-type doped layer of CEM is greater than a thickness of the second P-type doped layer of CEM, and
wherein the first write operation is asymmetric with the second write operation.

16. A method comprising:
forming first and second terminals on at least a portion of one or more contiguous layers of a correlated electron material (CEM) to form a correlated electron switch (CES), wherein the CES is capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation; and
affecting a structure or composition of the one or more contiguous layers of the CEM such that the first write operation is asymmetric with the second write operation, wherein affecting the structure or composition of the one or more contiguous layers of the CEM further comprises forming the one or more contiguous layers of the CEM to comprise at least an intrinsic layer of CEM between an N-type doped layer of CEM and a P-type doped layer of CEM.

17. A method comprising:
forming first and second terminals on at least a portion of one or more contiguous layers of a correlated electron material (CEM) to form a correlated electron switch (CES), wherein the CES is capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation; and
affecting a structure or composition of the one or more contiguous layers of the CEM such that the first write operation is asymmetric with the second write operation, wherein affecting the structure or composition of the one or more contiguous layers of the CEM furthe

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shifren Lucian
• Yeric Greg

Classifications

• G11C2213/73

  Array where access device function, e.g. diode function, being merged with memorizing function of memory element · CPC title

• H01L45/1641

  Electricity · mapped topic

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• H01L49/003 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic