Nanostructured LED

US10217917B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10217917-B2
Application numberUS-201715455403-A
CountryUS
Kind codeB2
Filing dateMar 10, 2017
Priority dateJul 7, 2008
Publication dateFeb 26, 2019
Grant dateFeb 26, 2019

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light-reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n-junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.

First claim

Opening claim text (preview).

The invention claimed is: 1. A flip-chip light emitting diode (LED) device comprising: a carrier wafer including a first conductive pad and second conductive pads on a top surface thereof: a buffer layer located over the carrier wafer and having a first surface that faces the top surface of the carrier wafer; multiple light emitting diodes (LEDs) located on areas of the first surface of the buffer layer and protruding downward toward the carrier wafer; light-reflecting or transparent contact layers located on a bottom side of a respective one of the multiple LEDs, wherein each of the LEDs includes a respective pn or p-i-n junction of which a first terminal is electrically connected to the buffer layer and of which a second terminal is electrically connected to a respective one of the light-reflecting or transparent contact layers; a group of contact pads located on a bottom surface of a respective one of the light-reflecting or transparent contact layers; and soldering bumps bonded to a respective one of the second conductive pads and to a respective one of the group of contact pads, wherein the buffer layer is electrically connected to the first conductive pad on the top surface of the carrier wafer through a conductive material. 2. The flip-chip LED device of claim 1 , wherein the areas are isolated areas that are laterally spaced among one another. 3. The flip-chip LED device of claim 1 , wherein the group of contact pads comprises a one-dimensional array that laterally extends along horizontal directions that are perpendicular to each other. 4. The flip-chip LED device of claim 3 , wherein each contact pad within the group of contact pads is electrically isolated among one another by an electrically insulating pattern located on the first surface of the buffer layer. 5. The flip-chip LED device of claim 1 , wherein the areas are arranged in a matrix pattern with a quadratic or rectangular shape and laterally displaced among one another. 6. The flip-chip LED device of claim 1 , wherein the conductive material that electrically connects the buffer layer to the first conductive pad is located below the buffer layer and above the first conductive pad. 7. The flip-chip LED device of claim 1 , wherein areas of the light-reflecting or transparent contact layers strictly define light emission areas. 8. The flip-chip LED device of claim 1 , wherein the multiple LEDs emit light upward through the buffer layer. 9. The flip-chip LED device of claim 1 , wherein the light-reflecting or transparent contact layers are light-reflecting layers. 10. The flip-chip LED device of claim 9 , wherein the light-reflecting layers comprises silver or aluminum. 11. The flip-chip LED device of claim 10 , further comprising a dielectric capping layer located on the bottom surfaces of the light-reflecting layers, wherein the group of contact pads contacts the light-reflecting layers through openings in the dielectric capping layer. 12. The flip-chip LED device of claim 11 , wherein the dielectric capping layer comprises a material selected from Si 3 N 4 , SiO 2 , and Al 2 O 3 . 13. The flip-chip LED device of claim 1 , wherein the group of contact pads have a lesser area than the light-reflecting or transparent contact layers. 14. The flip-chip LED device of claim 1 , wherein the light-reflecting or transparent contact layers comprise a Zn x O 1-x or In x Sn y O 1-x-y transparent contact layer. 15. The flip-chip LED device of claim 1 , wherein the buffer layer is light-transmissive. 16. The flip-chip LED device of claim 1 , wherein a phosphor is located over a second surface of the buffer layer, the second surface being located on an opposite side of the first surface of the buffer layer.

Assignees

Inventors

Classifications

  • by switching light sources (by switching incandescent light sources F21S41/162) · CPC title

  • comprising a two-dimensional [2D] array of point-like light-generating elements · CPC title

  • Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less · CPC title

  • Electromagnetic energy · CPC title

  • arranged in a matrix · CPC title

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Frequently asked questions

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What does patent US10217917B2 cover?
The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light-reflecting contact laye…
Who is the assignee on this patent?
Glo Ab
What technology area does this patent fall under?
Primary CPC classification H01L33/62. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).