Bipolar junction transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10217853-B1
Application number	US-201715717975-A
Country	US
Kind code	B1
Filing date	Sep 28, 2017
Priority date	Aug 28, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

First claim

The invention claimed is:

1. A bipolar junction transistor (BJT), comprising:
a substrate having an emitter region, a base region, and a collector region;
a shallow trench isolation (STI) between the emitter region and the base region;
a first well region disposed in the base region; and
a second well region disposed in the emitter region, wherein the first well region and the second well region comprise different concentration and same conductive type, the second well region is directly under part of the STI, and bottom surfaces of the first well region and the second region are coplanar.

2. The bipolar junction transistor of claim 1 , further comprising a deep well region under the emitter region, the base region, and the collector region.

3. The bipolar junction transistor of claim 2 , further comprising a third well region in the collector region.

4. The bipolar junction transistor of claim 3 , wherein the first well region and the second well region comprise a first conductive type and the deep well region and the third well region comprise a second conductive type.

5. The bipolar junction transistor of claim 4 , wherein the first conductive type comprises p-type and the second conductive type comprises n-type.

6. The bipolar junction transistor of claim 1 , further comprising fin-shaped structures on the substrate, wherein the first well region and the second well region are disposed in the fin-shaped structures.

7. The bipolar junction transistor of claim 6 , further comprising a gate structure on each of the emitter region, the base region, and the collector region.

Assignees

• United Microelectronics Corp

Inventors

• Pan Chen-Wei

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title