Manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10217749-B2
Application number	US-201815894947-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Mar 1, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor memory device, comprising:
providing a semiconductor substrate having a memory cell region and a peripheral region defined thereon;
forming bit line structures on the memory cell region;
forming at least one gate structure on the peripheral region;
forming a spacer layer covering the semiconductor substrate, the gate structure, and the bit line structures, wherein the spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region;
performing a first etching process to the spacer layer for removing a part of the spacer layer on the memory cell region, wherein at least a part of the spacer layer remains on the memory cell region after the first etching process; and
performing a second etching process after the first etching process for removing the spacer layer remaining on the memory cell region, wherein the first etching process is different from the second etching process, the first etching process comprises an anisotropic etching process, and the second etching process comprises an isotropic etching process.

2. The manufacturing method of the semiconductor memory device according to claim 1 , wherein the spacer layer covering the gate structure and the bit line structures in a vertical direction perpendicular to the semiconductor substrate is removed by the first etching process.

3. The manufacturing method of the semiconductor memory device according to claim 2 , further comprising:
forming a dielectric layer covering the bit line structures before the step of forming the spacer layer, wherein the first etching process is stopped at the dielectric layer.

4. The manufacturing method of the semiconductor memory device according to claim 3 , wherein the dielectric layer formed on the bit line structures in the vertical direction is covered by the spacer layer before the first etching process, and the dielectric layer formed on the bit line structures in the vertical direction is exposed after the first etching process.

5. The manufacturing method of the semiconductor memory device according to claim 3 , wherein the dielectric layer is further formed on the peripheral region, and the manufacturing method of the semiconductor memory device further comprises:
etching the dielectric layer formed on the peripheral region for forming a first spacer on sidewalls of the gate structure.

6. The manufacturing method of the semiconductor memory device according to claim 2 , wherein the spacer layer on the peripheral region is partially removed by the first etching process to become a second spacer on sidewalls of the gate structure.

7. The manufacturing method of the semiconductor memory device according to claim 6 , further comprising:
forming a patterned mask layer covering the gate structure and the second spacer on the peripheral region after the first etching process and before the second etching process, wherein the gate structure and the second spacer on the peripheral region are covered by the patterned mask layer during the second etching process.

8. The manufacturing method of the semiconductor memory device according to claim 7 , wherein the spacer layer on the memory cell region is not covered by the patterned mask layer during the second etching process.

9. The manufacturing method of the semiconductor memory device according to claim 2 , wherein the spacer layer on the memory cell region is partially removed by the first etching process to become third spacers on sidewalls of the bit line structures.

10. The manufacturing method of the semiconductor memory device according to claim 9 , wherein at least a part of the third spacers are removed by the second etching process.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chen Yu-Ching
• Tzou Shih-Fang
• Yu Kuei-Hsuan
• Chuang Hui-Ling

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H01L27/10897

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic

• H01L21/31144

  Electricity · mapped topic