Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures

Patent metadata

Field	Value
Publication number	US-10217644-B2
Application number	US-201213556217-A
Country	US
Kind code	B2
Filing date	Jul 24, 2012
Priority date	Jul 24, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
at least one semiconductor device comprising a semiconductor substrate;
a first dielectric layer having a top surface and a bottom surface,
wherein the bottom surface adjoins the semiconductor substrate;
geometric structures formed in the first dielectric layer,
wherein each of the geometric structures defines a respective blind hole in the first dielectric layer extending from the top surface to a respective intermediate surface of the first dielectric layer that is between the top surface and the bottom surface, and
at least one of the geometric structures has an undercut profile in the first dielectric layer, such that a cross-sectional gap width of the first dielectric layer increases, at least in part, from the top surface towards the respective intermediate surface; and
a conductive layer on the first dielectric layer,
wherein the conductive layer is at least located over the geometric structures and completely fills the geometric structures.

2. The semiconductor device structure of claim 1 , wherein the conductive layer comprises a bond pad.

3. The semiconductor device structure of claim 2 , wherein the bond pad is located over the geometric structures.

4. The semiconductor device structure of claim 1 , further comprising a second dielectric layer disposed over the conductive layer.

5. The semiconductor device structure of claim 1 , wherein the conductive layer comprises titanium (Ti).

6. The semiconductor device structure of claim 1 , wherein the first dielectric layer comprises boron phosphorus silicate glass (BPSG).

7. The semiconductor device structure of claim 1 , wherein the geometric structures have a depth ranging from 100-300 nm.

8. The semiconductor device structure of claim 1 , wherein the geometric structures have a spacing ranging from 2-15 μm.

9. The semiconductor device structure of claim 1 , wherein the geometric structures have a spacing formed in the range 15-30 μm.

10. The semiconductor device structure of claim 1 , wherein the geometric structures have a diameter formed in the range 1-5 μm.

11. A method of depositing a conductive layer on a semiconductor device, the method comprising:
providing at least one semiconductor device that comprises a semiconductor substrate;
forming a first dielectric layer on the at least one semiconductor device, wherein the first dielectric has a top surface and a bottom surface, wherein the bottom surface adjoins the semiconductor substrate;
forming a plurality of geometric structures in the first dielectric layer,
wherein each of the geometric structures defines a respective blind hole in the first dielectric layer extending from the top surface to a respective intermediate surface of the first dielectric layer that is between the top surface and the bottom surface, and
at least one of the geometric structures has an undercut profile in the first dielectric layer, such that a cross-sectional gap width of the first dielectric layer increases, at least in part, from the top surface towards the respective intermediate surface; and
depositing a first conductive layer on the first dielectric layer, such that the first conductive layer is at least located over the geometric structures and completely fills the geometric structures.

12. The method of depositing a conductive layer of claim 11 , wherein the plurality of geometric structures are formed at a depth between 100 and 300 nm.

13. The method of depositing a conductive layer of claim 11 , wherein the plurality of geometric structures are formed at a spacing ranging from 5-15 μm.

14. The method of depositing a conductive layer of claim 11 , wherein the plurality of geometric structures are formed at a spacing ranging from 15-30 μm.

15. The method of depositing a conductive layer of claim 11 , wherein the plurality of geometric structures are formed with a diameter in the range 1-5 μm.

16. The method of depositing a conductive layer of claim 11 , wherein the conductive layer comprises a bond pad located above the geometric structures.

17. The method of depositing a conductive layer of claim 11 , wherein the conductive layer comprises Ti.

18. The method of depositing a conductive layer of claim 11 , wherein the first dielectric layer comprises BPSG.

19. A semiconductor device structure, comprising:
at least one semiconductor device comprising a semiconductor substrate,
wherein a first bond pad is disposed on a first surface of the semiconductor substrate;
a first dielectric layer having a top surface and a bottom surface,
wherein the bottom surface of the first dielectric layer adjoins the semiconductor substrate at the first surface of the semiconductor substrate, and
the first dielectric layer defines a through-hole opening over at least a portion of the first bond pad;
geometric structures formed in the first dielectric layer,
wherein each of the geometric structures defines a respective blind hole in the first dielectric layer extending from the top surface to a respective intermediate surface of the first dielectric layer that is between the top surface and the bottom surface, and
at least one of the geometric structures has an undercut profile in the first dielectric layer; and
a conductive layer on the first dielectric layer,
wherein the conductive layer is at least located over the geometric structures and completely fills the geometric structures, and
the conductive layer further extends into the through-hole opening so as to electrically and mechanically connect to the first bond pad.

20. The semiconductor device of claim 19 ,
wherein the at least one of the geometric structures has said undercut profile, such that a cross-sectional gap width of the first dielectric layer increases, at least in part, from the top surface towards the respective intermediate surface.

Assignees

• Grille Thomas
• Hedenig Ursula
• Plagmann Joern
• Schoenherr Helmut
• Muth Ralph
• Infineon Technologies Ag

Inventors

• Grille Thomas
• Hedenig Ursula
• Plagmann Joern
• Schoenherr Helmut
• Muth Ralph

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title