Pulsed control line biasing in memory

Patent metadata

Field	Value
Publication number	US-10217520-B2
Application number	US-201715685309-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Dec 7, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

First claim

We claim:

1. An apparatus, comprising:
a voltage source configured to apply one program voltage pulse followed by another program voltage pulse to a word line during a programming operation, the word line connected to a memory cell;
pulsing circuitry configured to provide one waveform having a voltage which varies periodically according to one duty cycle during the applying of the one program voltage pulse to the word line, and another waveform having a voltage which varies periodically according to another duty cycle during the applying of the another program voltage pulse to the word line; and
a control circuit configured to connect the one waveform to the memory cell via one of a bit line and source line during the applying of the one program voltage pulse to the word line, and to subsequently connect the another waveform to the memory cell via one of the bit line and the source line during the applying of the another program voltage pulse to the word line.

2. The apparatus of claim 1 , wherein:
the one waveform has one effective voltage which allows programming of the memory cell at a relatively fast rate; and
the another waveform has another effective voltage which allows programming of the memory cell at a relatively slow rate.

3. The apparatus of claim 2 , wherein:
the one effective voltage is lower than the another effective voltage.

4. The apparatus of claim 2 , wherein:
the one effective voltage is lower than the another effective voltage by an amount which is a function of an assigned data state of the memory cell.

5. The apparatus of claim 4 , wherein:
the amount is relatively higher when the assigned data state is a relatively low data state among a plurality of data states.

6. The apparatus of claim 1 , wherein:
a transition from the one waveform to the another waveform occurs at a program loop in a set of program loops which is a function of an assigned data state of the memory cell.

7. The apparatus of claim 6 , wherein:
a transition from the one waveform to the another waveform occurs at a relatively low program loop of the set of program loops when the assigned data state is a relatively high data state among a plurality of data states.

8. The apparatus of claim 1 , wherein:
the control circuit is configured to categorize a programming speed of the memory cell and to connect the another waveform to the memory cell during the applying of the another program voltage pulse to the word line in response to the memory cell being categorized as a relatively fast programming memory cell.

9. The apparatus of claim 1 , wherein:
the control circuit is configured to categorize a programming speed of another memory cell and to connect the one waveform to the another memory cell during the applying of the another program voltage pulse to the word line in response to the another memory cell being categorized as a relatively slow programming memory cell.

10. The apparatus of claim 9 , wherein:
the memory cells have a same assigned data state.

11. The apparatus of claim 1 , further comprising:
a latch storing data which identifies an assigned data state of the memory cell, wherein the control circuit is responsive to the latches.

12. A method, comprising:
performing one set of program loops for one set of memory cells in a programming operation, performing each program loop of the one set of program loops comprises applying one series of pulses having one duty cycle to the one set of memory cells;
based on a programming progress of the memory cells of the one set of memory cells during the one set of program loops, identifying memory cells of the one set of memory cells with a relatively slow programming speed and memory cells of the one set of memory cells with a relatively fast programming speed; and
subsequently performing another set of program loops for the one set of memory cells in the programming operation, performing each program loop of the another set of program loops comprises applying the one series of pulses having the one duty cycle to the memory cells with the relatively slow programming speed while applying another series of pulses having another duty cycle to the memory cells with the relatively fast programming speed.

13. The method of claim 12 , wherein:
the one series of pulses is applied to each memory cell of the one set of memory cells via one of a respective bit line and source line;
the one series of pulses is applied to each memory cell of the memory cells with the relatively slow programming speed via one of a respective bit line and source line; and
the another series of pulses is applied to each memory cell of the memory cells with the relatively fast programming speed via one of a respective bit line and source line.

14. The method of claim 12 , wherein:
the one series of pulses is obtained by pulsing a direct current voltage at the one duty cycle; and
the another series of pulses is obtained by pulsing the direct current voltage at the another duty cycle.

15. The method of claim 12 , wherein:
the one duty cycle is lower than the another duty cycle.

16. An apparatus, comprising:
means for applying a series of program voltage pulses to a set of memory cells in a programming operation, the series of program voltage pulses comprising one set of program voltage pulses followed by another program voltage pulse;
means for pulsing a direct current voltage at one duty cycle to provide one waveform during each program voltage pulse of the series of program voltage pulses and during the another program voltage pulse;
means for pulsing the direct current voltage at another duty cycle to provide another waveform during the another program voltage pulse;
means for applying the one waveform to the set of memory cells during each program voltage pulse of the one set of program voltage pulses;
means for applying the one waveform to one memory cell of the set of memory cells during the another program voltage pulse; and
means for applying the another waveform to another memory cell of the set of memory cells during the another program voltage pulse.

17. The apparatus of claim 16 , wherein:
the means for applying the one waveform to the one memory cell comprises one decoder connected to the means for pulsing the direct current voltage at the one duty cycle and to the means for pulsing the direct current voltage at the another duty cycle; and
the means for applying the another waveform to the another memory cell comprises another decoder connected to the means for pulsing the direct current voltage at the one duty cycle and to the means for pulsing the direct current voltage at the another duty cycle.

18. The apparatus of claim 17 , further comprising:
a control circuit configured to provide a control signal to the one decoder for selecting the one waveform or the another waveform for the one memory cell and to provide a control signal to the another decoder for selecting the one waveform or the another waveform for the another memory cell.

19. The apparatus of claim 16 , further comprising:
means for determining a programming speed category of the one memory cell and a programming speed category of the another memory cell, wherein:
the means for applying the one waveform to the one memory cell is responsive to the programming speed category of the one memory cell; and
the means for applying the another waveform to the another memory cell is responsive to the programming speed category of the another memory cell.

20. The apparatus of claim 1 , w

Assignees

• Sandisk Technologies Llc

Inventors

• Masuduzzaman Muhammad
• Dutta Deepanshu
• Yuh Jong

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title