Systems and methods for generating physically unclonable functions from non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-10216965-B2
Application number	US-201415109747-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Jan 8, 2014
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.

First claim

What is claimed is:

1. A method for generating a physically unclonable bitstring, the method comprising:
programming cells in a memory array to a first state;
for each cell in the memory array, measuring by a voltage-to-digital converter a value corresponding to a respective analog entropy source;
digitizing by the voltage-to-digital converter the value for each cell;
determining an approximate median value corresponding to the digitized values;
programming cells in the memory array having a value greater than the approximate median value to a second state; and
generating a bitstring by reading the states of cells in the memory array.

2. The method of claim 1 , wherein the first state corresponds to a logical zero state and the second state corresponds to a logical one state.

3. The method of claim 1 , wherein the first state corresponds to a logical one state and the second state corresponds to a logical zero state.

4. The method of claim 1 , wherein the memory array includes a flash memory array.

5. The method of claim 4 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a threshold voltage of a memory cell.

6. The method of claim 1 , wherein the memory array includes a memristor memory array.

7. The method of claim 6 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a write operation.

8. The method of claim 7 , wherein measuring a voltage corresponding to a write operation includes transmitting the voltage to the voltage-to-digital converter.

9. The method of claim 1 , wherein the memory array includes a nanoelectromechanical system memory array.

10. The method of claim 9 , wherein determining a value corresponding to a respective analog entropy source includes measuring a bitline voltage.

11. A device for generating a physically unclonable bitstring, the device comprising:
an array of memory cells; and
circuitry configured to
program cells in the memory array to a first state;
measure a voltage-to-digital converter a value corresponding to a respective analog entropy source for each cell in the memory array;
digitize by the voltage-to-digital converter the value for each cell;
determine an approximate median value corresponding to the digitized values; and
program cells in the memory array having a value greater than the approximate median value to a second state.

12. The device of claim 11 , wherein the first state corresponds to a logical zero state and the second state corresponds to a logical one state.

13. The device of claim 11 , wherein the first state corresponds to a logical one state and the second state corresponds to a logical zero state.

14. The device of claim 11 , wherein the memory array includes a flash memory array.

15. The device of claim 14 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a threshold voltage of a memory cell.

16. The device of claim 11 , wherein the memory array includes a memristor memory array.

17. The device of claim 16 , wherein determining a value corresponding to a respective analog entropy source includes measuring a voltage corresponding to a write operation.

18. The device of claim 11 , wherein the voltage-to-digital converter includes one or more delay chains.

19. The device of claim 11 , wherein the memory array includes a nanoelectromechanical system memory array.

20. The device of claim 19 , wherein determining a value corresponding to a respective analog entropy source includes measuring a bitline voltage.

Assignees

• Stc Unm
• Univ Case Western Reserve

Inventors

• Plusquellic James
• Bhunia Swarup

Classifications

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C23/00 Primary

  Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor · CPC title