Hardware mechanism for performing atomic actions on remote processors

Patent metadata

Field	Value
Publication number	US-10216662-B2
Application number	US-201514866933-A
Country	US
Kind code	B2
Filing date	Sep 26, 2015
Priority date	Sep 26, 2015
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Embodiments of systems, apparatuses, and methods for remote action handling are describe. In an embodiment, a hardware apparatus comprises: a first register to store a memory address of a payload corresponding to an action to be performed associated with a remote action request (RAR) interrupt, a second register to store a memory address of an action list accessible by a plurality of processors, and a remote action handler circuit to identify a received RAR interrupt, perform an action of the received RAR interrupt, and signal acknowledgment to an initiating processor upon completion of the action.

First claim

We claim:

1. A hardware apparatus comprising:
a first register in a processor core to store a memory address of a payload corresponding to an action to be performed associated with a remote action request (RAR) interrupt;
a second register in a processor core to store a memory address of an action list accessible by a plurality of processors;
a remote action handler circuit to:
identify a received RAR interrupt,
access the action list to identify an action to be performed and access the payload associated with the identified action,
perform the action of the received RAR interrupt, and
signal acknowledgment to an initiating processor upon completion of the action.

2. The hardware apparatus of claim 1 , further comprising:
a translation lookaside buffer (TLB) of virtual to physical page translations.

3. The hardware apparatus of claim 2 , wherein the action is to be one of:
invalidate the entire TLB;
invalidate a single entry of the TLB;
invalidate a number of consecutive pages of the TLB; and
perform no action.

4. The hardware apparatus of claim 1 , further comprising:
a memory to store the payload and the action list.

5. The hardware apparatus of claim 1 , wherein the remote action handler circuit to signal acknowledgment by clearing the action associated with the RAR interrupt from the action list.

6. The hardware apparatus of claim 1 , wherein the remote action handler to call a dedicated hardware handler to perform the action.

7. The hardware apparatus of claim 1 , wherein the memory is further to store an indication of validity of the payload.

8. A method comprising:
identifying a received remote action request (RAR) interrupt;
accessing an action list to identify, an action to be performed, the action list accessible by a plurality of processors and an address of the action list stored in a first register of a processor of the plurality of processors;
accessing a payload list that is stored in a second register of the processor of the plurality of processor associated with the identified action;
performing the action of the received RAR interrupt; and
signaling acknowledgment to an initiating processor upon completion of the action.

9. The method of claim 8 , wherein the action to be one of:
invalidate an entire translation lookaside buffer (TLB);
invalidate a single entry of the TLB;
invalidate a number of consecutive pages of the TLB; and
perform no action.

10. The method of claim 8 , wherein the signaling of acknowledgment is by clearing the action associated with the RAR interrupt from the action list.

Assignees

• Intel Corp

Inventors

• Mishaeli Michael
• Ouziel Ido
• Chaikin Baruch
• Zach Yoav

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title