Extended platform with additional memory module slots per CPU socket and configured for increased performance

Patent metadata

Field	Value
Publication number	US-10216657-B2
Application number	US-201615283186-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

First claim

What is claimed:

1. An apparatus comprising:
a printed circuit board (PCB) defining a length and a width, the length being greater than the width;
a first row of elements on the printed circuit board, including a first memory region configured to receive at least one memory module;
a second row of elements on the PCB including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB; and
a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module;
wherein the second row of elements is positioned between the first row of elements and the third rows of elements.

2. The apparatus of claim 1 , wherein each of the memory regions configured to receive at least one memory module includes a plurality of memory module slots.

3. The apparatus of claim 1 , wherein the first memory region and the second memory region are each configured to accept 16 DIMMs.

4. The apparatus of claim 2 , wherein the printed circuit board includes first and second ends, and first and second sides, wherein the length is a distance from the first end to the second end, wherein the width is a distance from the first side to the second side, and wherein the memory module slots in each of the first and second memory regions extend a direction parallel to the first and second sides of the printed circuit board.

5. The apparatus of claim 1 , wherein the printed circuit board comprises a half width motherboard.

6. The apparatus of claim 1 , wherein the printed circuit board includes a high speed input/output (HSIO) link between the first memory region and at least one of the first CPU socket and the second CPU socket, the HSIO link including a transfer rate of at least 5 gigabits per second per pin.

7. The apparatus of claim 1 , further comprising a plurality of dual in-line memory modules positioned in each of the memory regions.

8. A method comprising:
providing a printed circuit board having a length and a width, the length being greater than the width;
positioning a first memory region in a first area of a printed circuit board, the first memory regions configured to accept at least one memory module;
positioning a first CPU socket and a second CPU socket in a second area of a printed circuit board, the first CPU socket and the second CPU socket being positioned side by side along the width of the printed circuit board; and
positioning a second memory region in a third area of the printed circuit board, the second memory region configured to accept at least one memory module;
wherein the second area of the printed circuit board is positioned between the first area of the printed circuit board and the third area of the printed circuit board.

9. The method of claim 8 , further comprising configuring the first and second memory regions to include memory module slots.

10. The method of claim 8 , further comprising configuring the memory regions so that the first memory region and the second memory region are each configured to accept 16 DIMMs.

11. The method of claim 8 , further comprising configuring the first memory region and the second memory region to each include a plurality of memory module slots that each extend along a direction parallel to a side of the printed circuit board that defines the length of the printed circuit board.

12. The method of claim 8 , further comprising positioning a plurality of DIMMs in each of the first and second memory regions, and positioning a CPU in each of the first and second CPU sockets.

13. The method of claim 12 , further comprising configuring the printed circuit board to include a high speed input/output (HSIO) link between at least some of the DIMNIS in the first memory region and the CPU in the first memory region, the HSIO link including a transfer rate of at least 5 gigabits per second per pin.

14. An apparatus comprising:
a printed circuit board (PCB) defining a length and a width, the length being greater than the width;
a first row of elements on the printed circuit board, including a first group of dual in-line memory modules (DIMIVIs);
a second row of elements on the printed circuit board, including a first central processing unit (CPU) and a second CPU positioned side by side along the width of the printed circuit board; and
a third row of elements, including a second group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements.

15. The apparatus of claim 14 , wherein the first and second groups of DIMMs each include 16 DIMMs.

16. The apparatus of claim 14 , wherein the DIMMs in the first and second groups of DIMIVIs extend along a direction parallel to a side of the PCB that defines the length of the printed circuit board.

17. The apparatus of claim 14 , wherein the printed circuit board comprises a half width motherboard.

18. The apparatus of claim 14 , further comprising a first high speed input/output (HSIO) link between the first CPU and a first subgroup of dual in-line memory modules (DIMMs) of the first group of DIMMS, the HSIO link including a transfer rate of at least 5 gigabits per second per pin.

19. The apparatus of claim 15 , wherein the first, second, and third rows of elements are positioned on the printed circuit board.

20. The apparatus of claim 19 , wherein the printed circuit board has a length in a range of 26 to 30 inches and a width in a range of 6 inches to 9 inches.

21. The apparatus of claim 19 , wherein the printed circuit board has a length in a range of 27.5 inches to 29 inches.

22. A system including the apparatus of claim 14 , wherein the printed circuit board is a first printed circuit board, the system comprising:
second, third, and fourth printed circuit boards, each including:
a first row of elements on the printed circuit board, including a first group of dual in-line memory modules (DIMMs);
a second row of elements on the printed circuit board, including a first central processing unit (CPU) and a second CPU positioned side by side along the width of the printed circuit board; and
a third row of elements, including a second group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements;

a first stack including the first printed circuit board stacked on the second printed circuit board; and
a second stack including the third printed circuit board stacked on the fourth printed circuit board;
wherein the first stack and the second stack are positioned side by side.

23. An apparatus comprising:
a printed circuit board defining a length and a width, the length being greater than the width;
a printed circuit board (PCB) including first, second, and third rows of elements;
the first row of elements on the PCB including a first CPU socket configured to receive a first CPU, a first memory region configured to receive at least one memory module, and a second memory region configured to receive at least one memory module, the first CPU socket positioned between the first memory region and the second memory region;
the second row of elements including a third memory region configured to receive at least one memory module;
the third row of elements including a second CPU socket configured to receive a second CPU, a fourth m

Assignees

• Intel Corp

Inventors

• Querbach Bruce
• Vogt Pete D

Classifications

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F1/18

  Packaging or power distribution · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G06F13/1678 Primary

  using bus width · CPC title