Hardware integrity verification

US10216625B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10216625-B2
Application numberUS-201313828661-A
CountryUS
Kind codeB2
Filing dateMar 14, 2013
Priority dateSep 24, 2012
Publication dateFeb 26, 2019
Grant dateFeb 26, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for storing digital data, comprising: a controller that is configured to: send commands including write commands and write data chunks associated with the write commands, wherein the write commands are tagged with sequence numbers and physical “PHY” channels to which the write commands are directed, and the write data chunks are tagged with a same sequence number as its corresponding write command; and a flash interface configured to: rece…

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What does patent US10216625B2 cover?
A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the da…
Who is the assignee on this patent?
Sk Hynix Memory Solutions Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).